In the early 1980s, Wolfgang Rosenstiel was a student of Computer Science at the University of Karlsruhe (KIT). During the next 40 years, we worked together at times, we met at numerous conferences and workshops, we visited each other regularly, and above all we became good friends. He was a person with an extraordinary capacity for work with a contagiously positive and optimistic outlook, an excellent researcher and teacher, involved in many aspects of our profession.

Moore's Law has driven the semiconductor revolution enabling over four decades of scaling in frequency, size, complexity, and power. However, the limits of physics are preventing further scaling of speed, forcing a paradigm shift towards multicore computing and parallelization. In effect, the system is taking over the role that the single CPU was playing: high-speed signals running through chips but also packages and boards connect ever more complex systems. High-speed signals making their way through the entire system cause new challenges in the design of computing hardware. Inductance, phase shifts and velocity of light effects, material resonances, and wave behavior become not only prevalent but need to be calculated accurately and rapidly to enable short design cycle times. In essence, to continue scaling with Moore's Law requires the incorporation of Maxwell's equations in the design process. Incorporating Maxwell's equations into the design flow is only possible through the combined power that new algorithms, parallelization and high-speed computing provide. At the same time, incorporation of Maxwell-based models into circuit and system-level simulation presents a massive accuracy, passivity, and scalability challenge. In this tutorial, we navigate through the often confusing terminology and concepts behind field solvers, show how advances in field solvers enable integration into EDA flows, present novel methods for model generation and passivity assurance in large systems, and demonstrate the power of cloud computing in enabling the next generation of scalable Maxwell solvers and the next generation of Moore's Law scaling of systems. We intend to show the truly symbiotic growing relationship between Maxwell and Moore!

Large-scale commodity computing coupled with services purchased over the internet (e.g. Software as a Service, SaaS), aka the cloud, are shifting the computing paradigm once again. Integrated circuit, package and board design is certainly being affected by this change and will, to some extent, migrate from workstations and corporate servers to the cloud. The effect of this change goes beyond the mere convenience of web-hosted design software and is profound. The main driving forces are cost-effectiveness and the exploitation of massive parallelism: The cloud gives the illusion of unlimited resources for a given amount of time, providing access to unprecedented capacity and speed on a pay-per-use basis. Over time a new generation of design technology, written from the ground up with parallelism and the cloud in mind, will emerge. This paper explores these issues in general, and examines a particularly good match for the cloud, namely electromagnetic field simulation..

Cloud computing is used to describe a collection of (remote) data centers (the hardware and the software) and applications delivered from them as a service (SaaS, Software as a Service). Its success is driven by the cost-effective on-demand availability of large, scalable amounts of computing resources. The cloud has become an established paradigm for many enterprise and consumer applications such as email, web servers, productivity applications, customer relationship management, etc. However, in IC design its success is still limited.

How can design teams employ new tools and develop response methodologies yet still stay within design budgets? How much effort does it require to be an early adopter and what kind of measurable results compensate for this effort? Panelists discuss how their design-for-manufacture (DFM) tools fit into a fixed design methodology, budget and timeline, and give examples of expected ROI (monetary, quality, reduced time-to-market, and comprehensive yield).The aim of this panel is to provide a serious comparison of related DFM technologies on the market and some idea of the cost and difficulty of integrating the tools into a fixed design budget and timeline. Specific results will be cited, along with examples of expected ROI (monetary, quality, reduced time-to-market, and comprehensive yield enhancement).The audience should walk away with enough information to make an informed decision on which companies would make sense for their DFM challenges, to reach their own yield and throughput goals.

Moore's law delivers higher performance and lower cost for FPGAs and ASICs alike, but at the 90nm process node and below, design schedules using the traditional cell-based ASIC design methodology hit a wall of uncertainty. At 90nm and below an emerging alternative ASIC design platform is either Platform ASIC or FPGAs. Which way will the cell-based ASIC designer turn for their next design?Over time, FPGAs and structured/platform ASICs are together poised to replace today's cell-based ASIC market, but which is the real answer to future digital design? Can companies really use these platforms to achieve the system cost reduction and functionality that they need to stay competitive? Which applications will migrate to these platforms the fastest? Is it possible to just tweak the existing cell-based methodology to more efficiently reach the benefits of 90nm process nodes and below? This lively panel will discuss whether it is FPGAs, structured/platform ASICs, or something else that stand to gain the most ground from the projected $25B ASIC market, and why.

A variety of business models in design and design automation are being employed today that have a dramatic effect on the success of individual companies and of multiple industries within the domain of electronics. The three talks in this session will study models for managing IP, software licensing, design and EDA services. A variety of approaches, constraints, and case studies will be presented in each talk, with conclusions about how to make these models most successful for all parties involved. The final portion of the session is devoted to discussion, debate, and Q&A.

Programmable circuit design has played an important role in improving design productivity over the last few decades. By imposing structure on the design, efficient automation of synthesis, placement and routing is possible. We focus on a class of programmable circuits known as mask programmable circuits. In this paper, we describe key issues in design and tool methodology that need to be addressed in creating a programmable fabric. We construct an efficient design flow that can explore different logic and routing architectures. The main advantage of our work is that we tailor tools designed for standard cell design, that are readily available in the market, to work on a programmable fabric. Our flow requires some additional software capability. A special router that understands programmable routing constructs to complete connections is described. In addition, a tool that packs logic efficiently after synthesis is also presented.

No abstract available.

The PC industry was the major consumer of silicon in the 80's and 90's. It defined the requirements for EDA. In a world dominated by PC's, clock frequency was the ultimate measure of performance. Times have changed. Today the internet, wireless communications and consumer applications such as high end gaming stations have replaced the PC as the primary driver. How we measure 'cutting edge' has also changed. Raw computing speed measured in terms of clock speed has given way to alternate forms of measuring performance - MBits/s, MMACS, and Polygons/sec now capture the differing computation requirements for these domains. Depending on the application domain, weight and power are just as important if not more important than raw computational power. How do these changes drive technology development in EDA? Which of these is the dominant EDA driver? How much of this drive is a function of EDA following the money? How much of this drive is a function of unique technical challenges posed by these domains? This diverse set of panelists with representation from various application segments and the EDA industry will attempt to answer these questions.

No abstract available.

It's been one year since Richard Goering told us that the EDA RTL-to-GDSII world was about to change. What have we learned? Who's winning, and who's not? This panel, consisting of the leading large and upcoming players in this space, will deliver concrete data to differentiate leading approaches to achieving design closure. Does the solution lie in raw speed and RTL optimization, with the synthesis-place-route back end just a commodity? Does the solution lie in new metrics for design convergence, and symmetric multiprocessing platforms for efficiency? Does the solution lie in a holistic, unified architecture of data model and tools? Or does the solution lie in extensions and unifications of existing production-proven logic, timing, and layout optimization technologies? A hard-hitting panel session will reveal the answers!

The automation of the design of electronic systems and circuits [electronic design automation (EDA)] has a history of strong innovation. The EDA business has profoundly influenced the integrated circuit (IC) business and vice-versa. This paper reviews the technologies, algorithms, and methodologies that have been used in EDA tools and the business impact of these technologies. In particular, we focus on four areas that have been key in defining the design methodologies over time: physical design, simulation/verification, synthesis, and test. We then look briefly into the future. Design will evolve toward more software programmability or some other kind of field configurability like field programmable gate arrays (FPGAs). We discuss the kinds of tool sets needed to support design in this environment.

No abstract available.

No abstract available.

Performance optimization of automatic test pattern generation (ATPG) algorithms has received considerable attention. While the application of high-performance algorithms is often limited to simple gates such as AND's, OR's, and XOR, the cell libraries of silicon vendors usually contain more sophisticated structures. To deal with this problem, we present a library independent algorithm for the partitioning and analysis of static digital CMOS circuits described at the switch level. The algorithm recognizes inverters, NANDs, and NORs. It also checks whether a partition can set its output to a high impedance state, thus being capable of partitioning large bus structures with tristate gates. Our approach supports existing ATPG algorithms at the gate level. Moreover, it allows a mixed-level approach for ATPG using detailed fault models at the switch level for whatever partitions it is necessary. Our implementation processes in the order of 2000 transistors per second. This is for circuits containing combinational and sequential logic on a state-of-the-art workstation. We processed complete chips with up to 72000 transistors, which is clearly adequate for practical purposes.

No abstract available.

The paper describes the design exploration environment of the CASTLE system. The environment allows the exploration of hardware and software for complex processor designs. The exploration is subdivided into the measurement phase and the analysis phase. The measurement phase uses a retargetable compiler to determine the performance for a large number of different processors and different programs. These fine-grained data form the input of the analysis phase. It transforms the data into abstract representations that are visualized for the designer. The results are integrated into an HTML-based framework.

In this paper we present a new data model for tool integration that extends existing data models by an abstract graph model.We provide a framework service based on this model which generates implementations of graph-based design representations from a conceptual schema.In two case studies we use them for rapid construction of a high-level synthesis tool and for easy fine-grained integration to an existing simulator. Tool Integration and Construction Using Generated Graph-Based Design RepresentationsAnsgar Bredenfeld

This paper describes SATISFAULT, a new hierarchical multilevel fault simulator with switch-level fault models and switch-level accuracy. SATISFAULT's intelligent scheduling mechanism switches between the abstraction levels to force simulation at the highest, thus fastest, possible level of abstraction without losing switch-level accuracy. The simulation algorithm is based on single fault-propagation for active faults. It deals with multiple abstraction levels and supports the inertial delay model. As a result, even large circuits may be fault-simulated accurately with all faults injected at the switch-level. Complete fault-simulation of all transistors stuck-on and stuck-open of circuits up to 105000 transistors including faults inside flip-flops is possible in reasonable time. In addition, SATISFAULT is also capable of simulating bridging faults for IddQ detectability.>

Design reuse is expected to be a key enabler for system designs in the 90's. Proponents claim that design reuse increases competitiveness through better quality, improved predictability and better productivity. On the other hand, skeptics say that design reuse is not realizable due to several barriers including rapid changes in technology, lack of standardized libraries and the presence of human, as opposed to technical barriers. Is design reuse a reality? How much is reused in practice? Where is it most applicable? Do concrete metrics exist for reusability? The panel will assess the track record of design reuse and discuss its status and future.

A good system design should balance the system resources in a way that achieves a high performance/cost ratio. In a quantitative approach the decisions upon the most suitable size for each component is based on measured analysis data. Using this approach for embedded system (ES) design requires the measurement of analysis data for a specific application domain. The paper presents the analysis environment of the CASTLE system. The environment supports measurement and visualization of analysis data for complex applications. As an example, the requirements analysis of an MPEG-1 video decoder is presented. The analysis data are used for specifying the structure of an embedded video compression system.>

This paper presents FEHSIM, a new hierarchical multi-level fault simulator with switch-level fault models and swttch-level accuracy.

As the scope of application of embedded CPUs changes, the design methodologies used to create embedded systems must keep pace. The authors explore what is understood of embedded system design, what problems need to be solved, and novel technologies that may help solve those problems.>

Article Data-path synthesis using path analysis Share on Authors: Reinaldo A. Bergamaschi IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, N.Y. IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, N.Y.View Profile , Raul Camposano IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, N.Y. IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, N.Y.View Profile , Michael Payer IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, N.Y. IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, N.Y.View Profile Authors Info & Claims DAC '91: Proceedings of the 28th ACM/IEEE Design Automation ConferenceJune 1991 Pages 591–596https://doi.org/10.1145/127601.127738Published:01 June 1991 16citation237DownloadsMetricsTotal Citations16Total Downloads237Last 12 Months0Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

A novel path-based scheduling algorithm is presented. It yields solutions with the minimum number of control steps, taking into account arbitrary constraints that limit the amount of operations in each control step. The result is a finite state machine that implements the control. Although the complexity of the algorithm is proportional to the number of paths in the control-flow graph, it is shown to be practical for large examples with thousands of nodes.>

High-level synthesis systems start with an abstract behavioral specification of a digital system and find a register-transfer level structure that realizes the given behavior. The various tasks involved in developing a register-transfer level structure from an algorithmic level specification are described. In particular, it is shown how the high-level synthesis task can be decomposed into a number of distinct but not independent subtasks. The techniques that have been developed for solving those subtasks are presented. Areas related to high-level synthesis that are still open problems are examined.>

The authors discuss in detail the synthesis of structures from behavioural domain descriptions. The overall synthesis approach is explained, the techniques and methods used to solve the main problems are discussed, implementation results are given, and experiences with various examples are described. The principal topics that are addressed are design description in the behavioural domain using a formal language, internal representation of the behaviour, synthesis based on data-flow analysis, optimizations and generation of a hardware structure. These techniques were implemented in the Karlsruhe DSL synthesis system.>