A CMOS analog circuit topology is presented that provides a number of stable operating points based on a laddered inverter quantizer (LIQAF) circuit. An input voltage sets the initial voltage state value when a CMOS transmission gate is turned on, and the voltage state then settles to the nearest stable operating point once the CMOS transmission gate is turned off. The proposed analog circuit achieves its stable operating levels through nonlinear, continuous-time feedback with a circuit that requires only a single supply voltage. An IC prototype demonstrates a 10-level version of the multi-stable circuit with an area of 0.015mm2in 0.18μm CMOS and current consumption of 300μA at 1.4V and <;45μA at 1V supply for a pair of the multi-stable circuits.

An 80 MS/s analog-to-digital converter (ADC) based on single-slope conversion is presented which utilizes a recently developed gated ring oscillator (GRO) time-to-digital converter (TDC) to achieve an ENOB of 6.45 bits. To save power, the time-to-digital conversion is done in two steps, the first of which is based on coarse time quantization as measured by cycles of an oscillator and the second of which is based on fine time quantization by the GRO TDC. The resulting 0.13 mum CMOS prototype circuit is simple and compact in its implementation and consumes 6.4 mW of power.

A voltage-controlled oscillator (VCO) based analog-to-digital converter (ADC) utilizing Sigma-Delta (Σ-Δ) techniques for second order quantization noise shaping is presented. A custom IC prototype of this highly digital architecture achieves 60-dB signal-to-noise ratio (SNR) over a 1-MHz bandwidth with 800-MHz sampling rate. It was fabricated in a 0.18-µm 1-poly 5-metal CMOS technology.

A new methodology for designing fractional-N frequency synthesizers and other phase locked loop (PLL) circuits is presented. The approach achieves direct realization of the desired closed loop PLL transfer function given a set of user-specified parameters and automatically calculates the corresponding open loop PLL parameters. The algorithm also accomodates nonidealities such as parasitic poles and zeros. The entire methodology has been implemented in a GUI-based software package, which is used to verify the approach through comparison of the calculated and simulated dynamic and noise performance of a third order fractional-N frequency synthesizer.

Techniques for fast and accurate simulation of fractionalN synthesizers at a detailed behavioral level are presented. The techniques allow a uniform time step to be used for the simulator, and can be applied to a variety of phase locked loop (PLL) and delay locked loop (DLL) circuits beyond fractional-N synthesizers, as well as to a variety of simulation frameworks such as Verilog and Matlab. Simulated results from a custom C++ simulator are shown to compare well to measured results from a prototype fractional-N synthesizer using a #-# modulator to dither its divide value.