OBJECTIVE: We discuss implications of potential ascertainment biases for studies examining diabetes risk following SARS-CoV-2 infection using electronic health records (EHRs). We quantitatively explore sensitivity of results to misclassification of COVID-19 status using data from the U.S.-based Diabetes in Children, Adolescents and Young Adults (DiCAYA) Network on children (≤17 years) and young adults (18-44 years). MATERIALS AND METHODS: In our retrospective case study from the DiCAYA Network, SARS-CoV-2 was identified using labs and diagnoses from June 1, 2020 to December 31, 2021. Patients were followed through December 31, 2022 for new diabetes diagnoses. Sites examined incident diabetes by COVID-19 status using Cox proportional hazards models. Results were pooled in meta-analyses. A bias analysis examined potential impact of COVID-19 misclassification scenarios on results, guided by hypotheses that sensitivity would be <50% and would be higher among those who developed diabetes. RESULTS: Prevalence of documented COVID-19 was low overall and variable across sites (children: 4.4%-7.7%, young adults: 6.2%-22.7%). Individuals with documented COVID-19 were at higher risk of incident diabetes compared to those with no documented infection, but results were heterogeneous across sites. Findings were highly sensitive to COVID-19 misclassification assumptions. Observed results could be biased away from the null under several differential misclassification scenarios. DISCUSSION: Although EHR-based documentation of COVID-19 was associated with incident diabetes, COVID-19 phenotypes likely had low sensitivity, with considerable variation across sites. Misclassification assumptions strongly impacted interpretation of results. CONCLUSION: Given the potential for low phenotype sensitivity and misclassification, caution is warranted when interpreting analyses of COVID-19 and incident diabetes using clinical or administrative databases.

There has been a recent push in extraction of 3D spatial layout of scenes. However, none of these approaches model the 3D interaction between objects and the spatial layout. In this paper, we argue for a parametric representation of objects in 3D, which allows us to incorporate volumetric constraints of the physical world. We show that augmenting current structured prediction techniques with volumetric reasoning significantly improves the performance of the state-of-the-art.

We study the problem of generating plausible interpretations of a scene from a collection of line segments automatically extracted from a single indoor image. We show that we can recognize the three dimensional structure of the interior of a building, even in the presence of occluding objects. Several physically valid structure hypotheses are proposed by geometric reasoning and verified to find the best fitting model to line segments, which is then converted to a full 3D model. Our experiments demonstrate that our structure recovery from line segments is comparable with methods using full image appearance. Our approach shows how a set of rules describing geometric constraints between groups of segments can be used to prune scene interpretation hypotheses and to generate the most plausible interpretation.

This paper presents a technique for automated design and optimization of low-noise oscillators. A sensitivity analysis for oscillators guides the reduction of oscillator noise intensities and improvement of oscillator's immunity to noise. A design-oriented approach to circuit analysis efficiently handles design constraints and reduces the dimensionality of the optimization problem. The perturbation projection vector based phase noise computation makes the proposed optimization technique general and applicable to all types of oscillators, independent of circuit topology. Several examples illustrate the benefits of the new optimization approach.

A new oscillator sensitivity analysis that predicts the impact of parameter variations of a VCO in a PLL is presented in this paper. Sensitivities of an oscillator's steady-state performance to design, process, or environmental parameter variations can be accurately and efficiently computed with the proposed analysis.

This paper presents an analysis for calculating sensitivities of an oscillator's periodic steady state and perturbation projection vector to design, process, or environmental parameters. A general continuous-time formulation and time-domain numerical methods are described. The applications of the oscillator sensitivity analysis in design optimization, macromodeling, as well as in analyzing the impact of process variations are demonstrated through examples.

This paper presents a generalized formulation of the periodic steady-state analysis for oscillators. The new formulation finds the value of a circuit parameter that results in a desired oscillation frequency for the circuit. Numerical methods based on the time-domain finite difference and shooting methods, and the frequency-domain harmonic balance method are described. Comparisons with search-based methods demonstrate the efficacy of the new approach.

This paper presents an analysis for calculating sensitivities of an oscillator’s periodic steady-state and perturbation projection vector to design, process, or environmental parameters. A general continuous- time formulation is described. Applications of the oscillator sensitivity analysis in design optimization and macromodeling are demonstrated through examples.

In this paper a modification of the time-domain periodic steady-state analysis for oscillators is presented. The proposed analysis finds the value of a circuit parameter that results in the circuit oscillating at a desired frequency. This analysis is based on the steady-state analysis for voltage and current controlled oscillators, i.e., replacing the oscillation period by a circuit parameter in the list of unknowns. A generalized formulation that can handle a control voltage or current, as well as any frequency-tuning circuit parameter, such as a tank capacitor or device geometry is developed in this paper.

This paper introduces the problem of finding the steady-state and the numerical value of the controlling voltage or current for oscillators where the frequency of oscillation is known beforehand. These situations are very common when the oscillator is part of a phase-locked loop (PLL). In PLLs, the reference frequency as well as the divide ratios are known at the time of design. Therefore the desired frequency of the voltage (current) controlled oscillator is known but not the controlling voltage (current). We formulate this problem as the solution of an appropriate nonlinear equation. We present robust and efficient numerical techniques for solving this nonlinear equation both in time and frequency domain. We demonstrate using experimental results that this technique is at par with classical methods of calculating oscillator steady-state and period of oscillation for a given control voltage. We show that compared to a search-based approach to calculating the desired control voltage or current, our direct method is a order of magnitude faster for the same accuracy.

The evolution of computer networking technology will likely require hardware that is flexible enough to adapt to changing standards while maintaining the highest possible performance. Much research has recently been done in active networks, which increase network flexibility by allowing the routers to be reprogrammed, often at the cost of lower throughput. A reconfigurable router implemented on a Custom Computing Machine (CCM) can provide the flexibility required for active networking while approaching the high throughput of inflexible application-specific integrated circuit (ASIC)-based routers. This paper presents an implementation of a prototype reconfigurable router on the Wildforce platform. The prototype implements IPv4 routing with a throughput of up to 576 Mbps, using a stream-based approach that facilitates dynamic reconfiguration.

Flexible and fast routers are generally considered a contradiction in terms since maintaining high-throughput requires fast but fixed-configuration application specific integrated circuits (ASICs) while flexibility requires slower but flexible configuration of general-purpose processors. A configurable stream-based reconfigurable router is a fast, flexible solution that includes the best features of both hardware and software processing through the efficient use of field-programmable gate array (FPGA) technology, active VHDL, and hardware/software partitioning and scheduling algorithms. This paper discusses the architecture of the stream-based reconfigurable router and presents the design, implementation, and evaluation of a prototype reconfigurable router.