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Junichi Yoshida

dblp:51/2089 · DBLP profile ↗
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5ranked-venue papers
0as first author
0since 2021 · last 2013
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 2Computer networks · 1Software engineering, systems software and programming languages · 1Theory of computation · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Software engineering, system software, and programming languages
1 paper
Software testing · 50% Empirical software engineering · 50%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Software testing › software validation
acceptance testing
0.212013
Assessing the Cost Effectiveness of Fault Prediction in Acceptance Testing · IEEE Trans. Software Eng. 2013
Empirical software engineering › software defect prediction
fault-prone module prediction
0.212013
Assessing the Cost Effectiveness of Fault Prediction in Acceptance Testing · IEEE Trans. Software Eng. 2013
Empirical software engineering
software defect prediction
0.212013
Assessing the Cost Effectiveness of Fault Prediction in Acceptance Testing · IEEE Trans. Software Eng. 2013
Software testing › test planning
test effort allocation
0.212013
Assessing the Cost Effectiveness of Fault Prediction in Acceptance Testing · IEEE Trans. Software Eng. 2013
Empirical software engineering
software effort estimation
0.012013
Assessing the Cost Effectiveness of Fault Prediction in Acceptance Testing · IEEE Trans. Software Eng. 2013
Software testing › test process
test cost reduction
0.012013
Assessing the Cost Effectiveness of Fault Prediction in Acceptance Testing · IEEE Trans. Software Eng. 2013

Methods — techniques the papers use, named apart from their topics

simulation modeling · 0.2
YearPublicationVenuePosition
2013 Assessing the Cost Effectiveness of Fault Prediction in Acceptance Testing
abstract
Until now, various techniques for predicting fault-prone modules have been proposed and evaluated in terms of their prediction performance; however, their actual contribution to business objectives such as quality improvement and cost reduction has rarely been assessed. This paper proposes using a simulation model of software testing to assess the cost effectiveness of test effort allocation strategies based on fault prediction results. The simulation model estimates the number of discoverable faults with respect to the given test resources, the resource allocation strategy, a set of modules to be tested, and the fault prediction results. In a case study applying fault prediction of a small system to acceptance testing in the telecommunication industry, results from our simulation model showed that the best strategy was to let the test effort be proportional to "the number of expected faults in a module × log(module size)." By using this strategy with our best fault prediction model, the test effort could be reduced by 25 percent while still detecting as many faults as were normally discovered in testing, although the company required about 6 percent of the test effort for metrics collection, data cleansing, and modeling. The simulation results also indicate that the lower bound of acceptable prediction accuracy is around 0.78 in terms of an effort-aware measure, Norm(Popt). The results indicate that reduction of the test effort can be achieved by fault prediction only if the appropriate test strategy is employed with high enough fault prediction accuracy. Based on these preliminary results, we expect further research to assess their general validity with larger systems.
Akito Monden, Takuma Hayashi, Shoji Shinoda, Kumiko Shirai, Junichi Yoshida, Mike Barker, Ken-ichi Matsumoto
IEEE Trans. Software Eng.5
2011 An Adaptive ICT Education Service based on Course Knowledge Database in Science and Technologies
Hiroto Yamakawa, Hiroshi Komatsugawa, Junichi Yoshida
ICCE3
2010 Sustainable Development and Maintenance of e-Learning Materials
Hiroto Yamakawa, Hiroshi Komatsugawa, Junichi Yoshida
ICCE3
2009 Proving Confluence of Term Rewriting Systems Automatically
Takahito Aoto 0001, Junichi Yoshida, Yoshihito Toyama
RTA2
2005 A 10 Gb/s wire-speed firewall system using reconfigurable processors
abstract
Although the Internet is playing an increasingly significant role in global communication, it remains vulnerable to malicious traffic such as worms and DoS/DDoS attacks. In the last few years, the emergence of high speed active worms, such as Code Red II, Nimda, SQL Slammer and MS Blaster, has become a serious issue. These worms cause serious damage to communication networks throughout the world by using up network bandwidth. In addition, since conventional firewall systems are located just in front of the server and do not prevent malicious traffic from entering the network, they cannot prevent such network congestion. We have developed a proto-type system of a network firewall using reconfigurable processors. In this paper, we overview the developed system and present its evaluation results.
Masaru Katayama, Hidenori Kai, Junichi Yoshida, Hiroki Yamada, Kohei Shiomoto, Naoaki Yamanaka
ICC3