Demo Data from VLDB 2026 / reviewers in the wild / expert
P. R. Miller
dblp:51/2975
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1989
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1Software engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Interconnection networks and networks-on-chip · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Interconnection networks and networks-on-chip › routing algorithms › adaptive routing
deadlock-free adaptive routing |
0.0 | 1 | 1989 | High Performance Communications in Processor Networks · ISCA 1989 |
Interconnection networks and networks-on-chip › routing algorithms
packet routing |
0.0 | 1 | 1989 | High Performance Communications in Processor Networks · ISCA 1989 |
Interconnection networks and networks-on-chip › multiprocessor interconnection
processor networks |
0.0 | 1 | 1989 | High Performance Communications in Processor Networks · ISCA 1989 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1989 | High Performance Communications in Processor NetworksabstractIn order to provide an arbitrary and fully dynamic connectivity in a network of processors, transport mechanisms must be implemented, which provide the propagation of data from processor to processor, based on addresses contained within a packet of data. Such data transport mechanisms must satisfy a number of requirements - deadlock and livelock freedom, good hot-spot performance, high throughput and low latency. This paper proposes a solution to these problems, which allows deadlock free, adaptive, high throughput packet routing to be implemented on networks of processors. Examples are given which illustrate the technique for 2-D array and toroidal networks. An implementation of this scheme on arrays of transputers is described. The scheme also serves as a basis for a very low latency routing strategy named the mad postman, a detailed implementation of which is described here as well. Chris R. Jesshope, P. R. Miller, Jay T. Yantchev |
ISCA | 2 |