Coarse-grained Reconfigurable Arrays (CGRAs) have become prevailing to accelerate regular kernels coupled with a host processor. As the end-to-end applications are increasingly complex, it is necessary to consider mapping whole programs onto a monolithic CGRA, to avoid the bottleneck of host communication implied by Amdahl’s law.State-of-the-art studies have developed compiling methods that spatially pipeline the whole program over hardware with many cores. However, these methods mainly focus on static reconfigurable dataflow architectures and fail to exploit the dynamic reconfiguration potential of dataflow architectures, resulting in suboptimal performance and underutilization of hardware resources. Nevertheless, it is nontrivial to generate a performant mapping on dynamic reconfigurable dataflow architectures since instruction-level deadlocks are introduced. To address this challenge, this paper proposes EDWAC, a whole-program compiler that generates high-quality configurations for dynamic reconfigurable dataflow architectures. EDWAC resolves the deadlock problem by a two-stage deadlock-prevention mechanism, which comprises a shared-resource-constrained Place and Route (PnR) stage, and a Finite State Machine(FSM)-based resource reallocation stage. Together with a gated control flow Intermediate Representation (IR) design and throughput-oriented optimization methods, EDWAC achieves exceptional resource utilization and PnR feasibility.

Modern out-of-order processors call for more aggressive scheduling techniques such as priority scheduling and out-of-order commit to make use of increasing core resources. Since these approaches prioritize the issue or commit of certain instructions, they face the conundrum of providing the capacity efficiency of scheduling structures while preserving the ideal ordering of instructions. Traditional collapsible queues are too expensive for today's processors, while state-of-the-art queue designs compromise with the pseudo-ordering of instructions, leading to performance degradation as well as other limitations.

Coarse-grained reconfigurable architecture (CGRA) has become a promising candidate for data-intensive computing due to its flexibility and high energy efficiency. CGRA compilers map data flow graphs (DFGs) extracted from applications onto CGRAs, playing a fundamental role in fully exploiting hardware resources for acceleration. Yet the existing compilers are time-demanding and cannot guarantee optimal results due to the traversal search of enormous search spaces brought about by the spatio-temporal flexibility of CGRA structures and the complexity of DFGs. Inspired by the amazing progress in reinforcement learning (RL) and Monte-Carlo tree search (MCTS) for real-world problems, we consider constructing a compiler that can learn from past experiences and comprehensively understand the target DFG and CGRA.