This paper presents the universal address sequence generator (UASG) for memory built-in-self-test. The studies are based on the proposed universal method for generating address sequences with the desired properties for multirun march memory tests. As a mathematical model, a modification of the recursive relation for quasi-random sequence generation is used. For this model, a structural diagram of the hardware implementation is given, of which the basis is a storage device for storing so-called direction numbers of the generation matrix. The form of the generation matrix determines the basic properties of the generated address sequences. The proposed UASG generates a wide spectrum of different address sequences, including the standard ones, such as linear, address complement, gray code, worst-case gate delay, $2^i$, next address, and pseudorandom. Examples of the use of the proposed methods are considered. The result of the practical implementation of the UASG is presented, and the main characteristics are evaluated.

Controlled random tests, methods of their generation, as well as their application to the testing of both hardware and software systems are discussed. Available evidences suggest that high computational complexity is one of the main drawback of these methods. Therefore we propose a technique to overcome this problem. In the paper, we introduce the concept of multiple controlled random tests ( MCRT) and examine various numerical characteristics in terms of the development of those tests. We prove the effectiveness of the Euclidean distance, as well as we propose an easy computational method of its calculation, in the process of constructing MCRT. The presented approach is evaluated through the experimental study in the context of testing of Random Access Memory (RAM).

Antirandom testing is a variation of pure random testing, which is the process of generating random patterns and applying it to a system under test (both software systems and hardware systems). However, research studies have shown that pure random testing is relatively less effective at fault detection than other testing techniques. Antirandom testing improves the fault-detection capability of random testing by employing the location information of previously executed test cases. In antirandom testing we select test case such that it is as different as possible from all the previous executed test cases. Unfortunately, this method essentially requires enumeration of the input space and computation of each input pattern when used on an arbitrary set of existing test data. This avoids scale-up to large test sets and (or) long input vectors. The objective of this paper is to find a more efficient method of the test generation which does not need any computation. The key idea of proposed approach is an iterative application of the short antirandom tests where the first test vector in each iteration is generated randomly. Moreover, we propose a new metric the Maximal Minimal Hamming Distance (MMHD) which allows us to define an optimal antirandom test with restricted number of patterns. Experimental results are given to evaluate the performance of the new approach.

Antirandom testing has proved useful in a series of empricial evaluations. It improves the fault-detection capability of random testing by employing the location information of previously executed test cases. In antirandom testing we select test pattern (test vector) such that it is as different as possible from all the previous executed test cases. Unfortunately, this method essentially requires enumeration of the input space and computation of each input vector when used on an arbitrary set of existing test data. This avoids scale-up to large test sets and (or) long input vectors. In this paper, we propose a new algorithm for antirandom test generation that is computationally feasible for BIST (Built In Self Test) tests. As the fitness function we use Maximal Minimal Hamming Distance (MMHD) rather than standard Hamming distance as is used in the classical approach. This allows to generate the most efficient test vectors in term of weighted number of generated k-bits tuples. Experimental results are given to evaluate the performance of the new approach.

This paper presents an integrated approach for both built-in online and off-line testing of embedded DRAMs. It is based on a new technique for output data compression which offers the same benefits as signature analysis during off-line test, but also supports efficient online consistency checking. The initial fault-free memory contents are compressed to a reference characteristic and compared to test characteristics periodically. The reference characteristic depends on the memory contents, but unlike similar characteristics based on signature analysis, it can be easily updated concurrently with WRITE operations. This way, changes in memory do not require a time consuming recomputation. The respective test characteristics can be efficiently computed during the periodic refresh operations of the dynamic RAM. Experiments show that the proposed technique significantly reduces the time between the occurrence of an error and its detection. Compared to error detecting codes (EDC) it also achieves a significantly higher error coverage at lower hardware costs. Therefore, it perfectly complements standard online checking approaches relying on EDC, where the concurrent detection of certain types of errors is guaranteed, but only during READ operations accessing the erroneous data.

The paper introduces the new concept of symmetric transparent BIST for RAMs. This concept allows one to skip the signature prediction phase of conventional transparent BIST approaches and therefore yields a significant reduction of test time. The hardware cost and the fault coverage of the new scheme remain comparable to that of a traditional transparent BIST scheme. In many cases, experimental studies even show a higher fault coverage obtained in shorter test time.

This paper presents a new technique for on-line consistency checking of embedded DRAMs. The basic idea is to use the periodic refresh operation for concurrently computing a test characteristic of the memory contents and compare it to a precomputed reference characteristic. Experiments show that the proposed technique significantly reduces the time between the occurrence of an error and its detection (error detection latency). It also achieves a very high error coverage at low hardware costs. Therefore it perfectly complements standard on-line checking approaches relying on error detecting codes, where the detection of certain types of errors is guaranteed, but only during READ operations accessing the erroneous data.

March algorithms are widely used in DRAM testing. They are relatively simple yet providing high fault coverage especially with respect to stuck-at faults, address uniqueness faults, and some types of cell-interaction faults. At the same time the capability of traditional March tests to detect pattern-sensitive faults is rather limited. This paper proposes an approach to enhance March test detection capability with respect to the pattern-sensitive faults.

After write operations, BIST schemes for RAMs relying on signature analysis must compress the entire memory contents to update the reference signature. This paper introduces a new scheme for output data compression which avoids this overhead while retaining the benefits of signature analysis. The proposed technique is based on a new memory characteristic derived as the module-2 sum of all addresses pointing to non-zero cells. This characteristic can be adjusted concurrently with write operations by simple EXOR-operations on the initial characteristic and on the addresses affected by the change.

Many march tests have already been designed to cover faults of different fault models. The complexity of these tests arises when linked faults are taken into consideration. This paper gives an overview of the most important and commonly used fault models, including the industry's popular disturb fault model. The fault coverage of march tests is analysed in a novel way, i.e., in terms of their detection capabilities for: simple faults, and linked faults; whereby the infinite class of linked faults has been reduced to a set of realistic linked faults. Thereafter the paper presents a methodology to design tests for realistic linked faults, resulting in the new tests March LR, March LRD and March LRDD. These new tests will be shown to be more efficient and to offer a higher fault coverage than comparable existing tests.

In this paper we illustrate that exact aliasing computation in RAM BIST can be achieved with respect to accurate RAM fault models including single and multiple stuck-at, transition and coupling cell-array faults and decoder stuck-at faults.

This paper presents a new methodology for RAM testing based on PS(n, k) fault model (the k out of n pattern sensitive fault model). According to the model the contents of any memory cell which belongs to an n-bit memory block, or ability to change the contents, is influenced by the contents of any k-1 cells from this block. This paper includes the investigation of memory testing approaches based on the transparent pseudoexhaustive testing and its approximations by pseudorandom circular tests, which can be used for periodic and manufacturing testing and require lower hardware and time overheads than the standard approaches.

Signature analyzers are very efficient output response compactors in BIST techniques. The only limitation of signature analysis is the fault coverage reduction (aliasing) due to the information loss inherent to any data compaction. In this paper, in order to increase the effectiveness of RAM BIST, we fake advantage from the regularity of the RAM test algorithms and we show that aliasing-free signature analysis can be achieved in RAM BIST.