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Katsuro Wakai

dblp:51/5404 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 1991
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 77% Processor architecture and microarchitecture · 23%

Topics — the 2 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
timing-driven design		 0.011991
Basic Concepts of Timing-oriented Design Automation for High-performance Mainframe Computers · DAC 1991
Processor architecture and microarchitecture › general-purpose processor architecture
mainframe processor design		 0.011991
Basic Concepts of Timing-oriented Design Automation for High-performance Mainframe Computers · DAC 1991

Methods — techniques the papers use, named apart from their topics

timing-driven placement and routing · 0.0
YearPublicationVenuePosition
1991 Basic Concepts of Timing-oriented Design Automation for High-performance Mainframe Computers
abstract
This paper outlines the concepts and the key technologies for designing high-performance mainframe computers.The goals of the design automation system are:1) reducing the development period, 2) implementing high performance.We perceive that both of the goals must be achieved for the timely development of mairtframe computers that meet the market demand.The latest high-performance mainframe computer, the Hitachi M-880, was successfully designed by utilizing this system, and total capability of the system has been proven.
Hidekazu Terai, Fumio Goto, Katsuro Wakai, Tokinori Kozawa, Mitsugu Edagawa, Satoshi Hososaka, Masahiro Hashimoto
 DAC3
1991 Logic Design for a High Performance Mainframe Computer, The HITAC M-880 Processor
abstract
Logic design and its effects on the HITAC M-880 basic scalar processor are described. The M-880 is a high end mainframe computer which uses current high speed circuits and packaging technologies, as well as logic methods, to improve performance. An optimal pipeline stage evaluation method is proposed, together with a new cache access method termed merge access. The combined effect of the logic methods is a 10% improvement in processor performance with online transaction processing.>
Yooichi Shintani, Kiyoshi Inoue, Toru Shonai, K. Wada, S. Abe, Katsuro Wakai
 ICCD6