There is a growing concern about the increasing vulnerability of future computing systems to errors in the underlying hardware. Traditional redundancy techniques are expensive for designing energy-efficient systems that are resilient to high error rates. We present Error Resilient System Architecture (ERSA), a robust system architecture which targets emerging killer applications such as recognition, mining, and synthesis (RMS) with inherent error resilience, and ensures high degrees of resilience at low cost. Using the concept of configurable reliability, ERSA may also be adapted for general-purpose applications that are less resilient to errors (but at higher costs). While resilience of RMS applications to errors in low-order bits of data is well-known, execution of such applications on error-prone hardware significantly degrades output quality (due to high-order bit errors and crashes). ERSA achieves high error resilience to high-order bit errors and control flow errors (in addition to low-order bit errors) using a judicious combination of the following key ideas: 1) asymmetric reliability in many-core architectures; 2) error-resilient algorithms at the core of probabilistic applications; and 3) intelligent software optimizations. Error injection experiments on a multicore ERSA hardware prototype demonstrate that, even at very high error rates of 20 errors/flip-flop/108cycles (equivalent to 25000 errors/core/s), ERSA maintains 90% or better accuracy of output results, together with minimal impact on execution time, for probabilistic applications such as K-Means clustering, LDPC decoding, and Bayesian network inference. In addition, we demonstrate the effectiveness of ERSA in tolerating high rates of static memory errors that are characteristic of emerging challenges related to SRAMVccminproblems and erratic bit errors.

There is a growing concern about the increasing vulnerability of future computing systems to errors in the underlying hardware. Traditional redundancy techniques are expensive for designing energy-efficient systems that are resilient to high error rates. We present Error Resilient System Architecture (ERSA), a low-cost robust system architecture for emerging killer probabilistic applications such as Recognition, Mining and Synthesis (RMS) applications. While resilience of such applications to errors in low-order bits of data is well-known, execution of such applications on error-prone hardware significantly degrades output quality (due to high-order bit errors and crashes). ERSA achieves high error resilience to high-order bit errors and control errors (in addition to low-order bit errors) using a judicious combination of 3 key ideas: (1) asymmetric reliability in many-core architectures, (2) error-resilient algorithms at the core of probabilistic applications, and (3) intelligent software optimizations. Error injection experiments on a multi-core ERSA hardware prototype demonstrate that, even at very high error rates of 20,000 errors/second/core or 2×10-4error/cycle/core (with errors injected in architecturally-visible registers), ERSA maintains 90% or better accuracy of output results, together with minimal impact on execution time, for probabilistic applications such as K-Means clustering, LDPC decoding and Bayesian networks. Moreover, we demonstrate the effectiveness of ERSA in tolerating high rates of static memory errors that are characteristic of emerging challenges such as Vccmin problems and erratic bit errors. Using the concept of configurable reliability, ERSA platforms may also be adapted for general-purpose applications that are less resilient to errors (but at higher costs).

Nanotechnology promises to open up new ways of scaling CMOS circuits by introducing new materials. For example, a hybrid circuit of CMOS gates and carbon nano-tubes (CNT), NEMS relay logic and emerging memory devices have been proposed for future nano-scale Field Programmable Gate Arrays (FPGAs). Hybrid circuits for use as FPGA configurable logic blocks (CLBs) are often proposed in the form of crossbar array architecture. However, many of emerging devices, such as NEMS relays, are not two terminal devices and are thus difficult to be used in the crossbar. On the other hand diode-based logics that are two-terminal devices that can be used in the crossbars, lack signal gain and inversion capability, which makes logic implementation with them difficult. We present nano-magnet/CMOS hybrid circuit using Magnetic Coupled Spin-Torque Devices (MCSTDs) to solve the signal gain and signal level restoration problems, allowing a crossbar array layout to be used throughout the entire crossbar array architecture FPGA. MCSTD consists of two spin torque input devices at the perimeter of a larger output device that serve as biasing dots and manipulate the magnetic reversal energy barrier of the center spintorque device. MCSTDs can implement entire Boolean logic (NAND, NOR, XOR, XNOR and NOT) simply by changing the location of the input spin-torque device and the magnetic shape anisotropy of the center device. The unique features of this logic include: 1) nonvolatility, 2) electronic gain for fan-out and signal restoration and 3) fewer devices to realize most logic functions (i.e. a single MCSTD gate can realize the entire range of Boolean logic gates, while CMOS takes up to 4 (NAND, NOR) or 16 (XOR, XNOR) transistors). The combination of non-volatility and smaller device count leads to reduced circuit area and lower power consumption. Signal gain is achieved by using asymmetric device dimensions between input and output devices. Area and energy consumption calculation of FPGA Look-Up Table (LUT) are performed to demonstrate the merits of the presented Nano-magnetic/CMOS hybrid circuit compared to CMOS. The results show a 94% savings in area at comparable energy consumptions when compared with 32nm CMOS technology node.

A large class of robust electronic systems of the future must be designed to perform correctly despite hardware failures. In contrast, today's mainstream systems typically assume error-free hardware. Classical fault-tolerant computing techniques are too expensive for this purpose. This paper presents an overview of new techniques that can enable a sea change in the design of cost-effective robust systems. These techniques utilize globally-optimized cross-layer approaches, i.e., across device, circuit, architecture, runtime, and application layers, to overcome hardware failures.

We present Sequoia, a programming language designed to facilitate the development of memory hierarchy aware parallel programs that remain portable across modern machines featuring different memory hierarchy configurations. Sequoia abstractly exposes hierarchical memory in the programming model and provides language mechanisms to describe communication vertically through the machine and to localize computation to particular memory locations within it. We have implemented a complete programming system, including a compiler and runtime systems for Cell processor-based blade systems and distributed memory clusters, and demonstrate efficient performance running Sequoia programs on both of these platforms.