This paper presents a SystemVerilog-based modeling and simulation methodology for a 4-level pulse-amplitude-modulation (PAM-4) transceiver. The framework is developed to address verification challenges in complex analog-to-digital converter (ADC)-based mixed-signal systems, where conventional circuit-level simulations suffer from prohibitively long execution time. Two key modeling techniques to significantly improve simulation efficiency are introduced in this work. For the time-interleaved ADC (TI-ADC), a counter-based equivalent circuit model is employed to capture dominant rank-1 mismatch errors while substantially reducing modeling complexity. In addition, for digital clock and data recovery (CDR), a statistical bit-error-rate (BER) evaluation approach based on XMODEL primitives is adopted as an alternative to conventional time-domain analog-mixed-signal (AMS) simulations. This modeling framework enables accurate verification of critical transceiver performance metrics, such as jitter tolerance (JTOL), within a 30-minute simulation window. Compared to conventional timedomain simulations, which require more than 12 hours to perform, the proposed approach achieves approximately a 24× improvement in simulation speed.

This paper presents a reconfigurable and energy-efficient digital spectrum shaping signaling (DSSS) for multidrop interfaces, where the output spectrum of the transmitted data is shaped using the 2-times repetitive block transmission to avoid frequency notches in the multidrop channel, thereby achieving a data rate up to 4× the first channel notch frequency. In conventional wireline transceivers (TRX), compensating for frequency notches requires a large number of decision feedback equalizer (DFE) taps at the receiver, resulting in significant area and power overhead. In contrast, the proposed DSSS architecture supports spectrum-efficient reconfigurable dual-mode NRZ/PAM-4, reducing required equalization efforts and improving energy efficiency. The proposed scheme and its transmitter (TX) were first validated through event-driven behavioral simulations using XMODEL and verified with equipment-based measurements. Post-layout simulation results in 28 nm CMOS process demonstrated 4 Gb/s data rate communicating over a channel having its first > 30 dB notch at 1 GHz, with a 235 mV vertical eye opening and a TX energy efficiency of 0.39 pJ/b at 0.8 V supply.

This article presents a 2-lane$2 \times 2$multiple-input, multiple-output (MIMO) 4-level pulse amplitude modulation (PAM-4) minimum mean-squared-error (MMSE)-decision-feedback equalizer (DFE) with far-end crosstalk (FEXT) cancellation for digital-to-analog converter (DAC)-/analog-to-digital converter (ADC)-based high-speed serial links. The receiver (RX) datapath is designed with a 15-tap MIMO feedforward equalizer (FFE) and a one-tap MIMO DFE with the least mean square (LMS), enabling adaptation to channel variation while maintaining the MMSE setting. The RX digital signal processor (DSP) place and route (PnR) in a 28-nm CMOS is estimated to consume 201 mW/lane at a 56-Gb/s/lane data rate while occupying a 0.5-mm2/lane silicon area. We further implement a real-time evaluation platform to verify the functionality of the MIMO PAM-4 MMSE-DFE with rapid bit-error-rate (BER) testing on RFSoC. The measurement result demonstrates that the MIMO MMSE-DFE significantly improves BER performance from 2.75e−3to 1.31e−7compared with equalization without FEXT cancellation when communicating over a channel exhibiting 12.4-dB insertion loss (IL) and 13.2-dB IL-to-crosstalk ratio (ICR) at Nyquist.

This work presents a multi-lane transceiver (TRX) architecture with discrete multitone (DMT) modulation for pin-efficient high-bandwidth chip-to-chip wireline communication. The proposed signaling uses 4 wires to transmit 3 lanes of DMT-modulated symbols in parallel including one lane for signal encoding and decoding for the correlated noise cancellation. Compared to the pin-efficiency of 0.5 in differential signaling, the proposed signaling offers a pin-efficiency of 0.75 allowing each TRX lane to operate at a lower speed given a fixed data throughput or to increase the per-pin data rate with the same or even lower per-lane data rate to differential signaling. While each single-ended lane includes random noise, the receiver (RX) can effectively eliminate most of the correlated noise with simple arithmetic in the digital domain. Higher pin efficiency can be achieved with more single-ended data lanes per redundancy lane depending on the link specifications such as raw bit-error-rate (BER), and voltage-domain dynamic range of the transmitter’s driver and the receiver. Simulation results show that 28.5% of throughput gain can be achieved with 3-lane 4-wire configuration given the same channel, analog front-end circuits, and noise condition to multi-lane differential DMT TRXs.

This paper presents an area- and energy-efficient 4-lane far-end crosstalk (FEXT) cancellation wireline transceiver (TRX) with a multiple-input multiple-output (MIMO) discrete multitone (DMT) modulation. The channel estimation (CHEST) is an essential block for DMT TRX to find the MIMO equalizer coefficients at the receiver (RX) side. However, due to the high computational complexity, the matrix inversion in CHEST hinders the generalization to larger MIMO, such as 4×4, considering circuit implementation. In this work, we show that CHEST can be effectively approximated to an element-wise reciprocal instead of an inversion when some properties of the wireline channels are used as constraints. This approximation also simplifies the MIMO equalizer circuit and realizes a decentralized MIMO. Simulation results demonstrated that the FEXT noise from adjacent lanes is sufficiently canceled out even with our approximated CHEST and MIMO equalizer, achieving a symbol error rate (SER) of 2E-4 for communicating over a channel exhibiting insertion loss (IL) of 16 dB and 17 dB of IL-to-crosstalk ratio at Nyquist, while showing SER of 1e-1 when the FEXT is not canceled.

This paper presents a novel digital decision feedback equalizer (DFE) design that can relax the feedback timing constraints for analog-to-digital converter (ADC)-based high-speed wireline receivers. The proposed technique breaks the loop-unrolled DFE (LU-DFE) chain by computing multiple LU-DFE chains in parallel with all possible seed symbols, and selecting the appropriate output by the post-processing selection logic. The proposed loop-break DFE (LB-DFE) is functionally equivalent to the conventional DFE with any other implementation techniques such as LU-DFE, look-ahead DFE (LA-DFE), or direct DFE. With topographical synthesis in 28nm CMOS process, the proposed LB-DFE achieved up to 54% of DFE area saving as compared to LA-DFE with look-ahead factor (LF) of 16 for 112Gb/s PAM-4 with 875MHz DSP clock speed. The implementation feasibility and functionality are verified using ZCU111 RFSoC platform at 6Gb/s (3GS/s ADC conversion rate) with a channel exhibiting 25dB loss at 1.5GHz, demonstrating the same bit error rate (BER) performance between the LB-DFE and the LA-DFE. Equipment-based measurements using arbitrary waveform generator (AWG) and real-time oscilloscope transmitting/receiving 40GBaud PAM-4 (80Gb/s) to/from the differential cables with software 21-tap feed-forward equalizer (FFE) and LB-DFE on PC was also conducted.

Full-waveform inversion (FWI) aims at building a high-resolution velocity model by fitting numerically computed seismic data to observed one. Considering both the kinematic and dynamic properties of all waves in seismic data makes FWI highly non-linear. To mitigate its non-linearity, one can preferentially build low-wavenumber background velocity first, and then retrieve high-wavenumber reflectivity. However, in the early stage of FWI, the low-wavenumber velocity update is hardly derived from the reflected waves and mainly relies on the diving waves. To secure a wider coverage of low-wavenumber velocity updates from the reflected waves in addition to the diving waves, we propose two-step FWI based on diffraction-angle filtering (DAF) for 3-D seismic reflection data. In our method, DAF, which imitates the amplitude variations of the PP partial derivative wavefields with respect to the model parameters in elastic FWI to control small, intermediate, or large diffraction-angle energy, is adopted for the scale separation of a given velocity model into a background velocity and reflectivity model. The prior reflectivity provides information on reflection wavepaths. Then, the low-wavenumber update generated along the full wavepaths can build a background velocity model with improved wavenumber coverage. In addition, DAF can be implemented without a large increase in computational effort, which enables practical applications of our method to large-scale 3-D seismic field data. Applications of DAF-based two-step FWI to 3-D synthetic and field seismic data demonstrate that DAF-based two-step FWI can build a reliable background velocity model, which leads to stable convergence toward the global minimum.

In 4-D seismic surveys performed for carbon capture and sequestration projects, it is essential to acquire consistent time-lapse data to track the behavior of carbon dioxide. However, in practice, seismic events affected by nonrepeatable effects (i.e., nonrepeatable noise) hinder the objective of these surveys. Cross-equalization (XEQ) is a task that aims to reduce differences between time-lapse data by alleviating the adverse effect of nonrepeatable noise. XEQ using a convolutional neural network was proposed and applied to poststack data. By utilizing masks derived from the eikonal equation, we design an XEQ method for prestack data, which could contribute to retrieving ancillary information impaired during stacking and migration. The inherent nature of prestack data poses challenges when changing the data domain. To address these challenges, we introduce three supplementary methods: Fourier loss, coordinate conditioning, and logarithmic rescaling. Numerical examples show that the proposed XEQ effectively suppresses nonrepeatable noise while preserving 4-D signals even for prestack data, with minimal impact on amplitude information representing the degree of change. In addition, the supplementary methods enhance the matching quality and training stability. Sensitivity analyses on several factors (i.e., seawater velocity, source characteristics, ambient noise, and inaccurate masks) demonstrate the robustness of the proposed XEQ in suppressing nonrepeatable noise.

The “CRC” service optimizes cross-region data copying for enhanced cost efficiency, progressing through three distinctive phases. During phase 1, an essential pipeline is established to fulfill functional prerequisites while ensuring robust security standards. In phase 2, cost-efficiency is amplified by decreasing execution frequency, a strategy encompassing subphases: a) exclusion of unaltered tables, b) deferred scheduling facilitated by modification timestamp logging, and c) projection of execution durations to guarantee data timeliness. In phase 3, the spotlight shifts to minimizing scanned data for partitioned tables, leveraging phase 2’s algorithmic expansion from tables to partitions. Evaluation results underscore the service’s tangible impact, displaying significant cost reduction across frequently accessed datasets.