This paper presents an analog RF-domain implementation of a Vanilla Recurrent Neural Network (RNN) for real-time anomaly detection in 5G and beyond wireless networks. Real-time analysis is crucial to distinguish benign irregularities from true anomalies that may indicate malicious activity or network issues. The proposed design leverages passive components, such as switches and capacitors, enabling low-latency processing directly at RF frequencies. Circuit simulations validate the approach, achieving up to 89% accuracy across three anomaly classes, demonstrating the potential of RF-domain neural networks for fast and efficient wireless signal analysis.

We propose a sustainable federated learning (FL)-based monitoring system, namely susFL, for smart animal farms to address the challenge of inconsistent health monitoring due to fluctuating energy levels of solar sensors. This system equips animals, such as cattle, with solar sensors with computational capabilities, including Raspberry Pis, to train a local deep-learning model on health data. These sensors periodically update Long Range (LoRa) gateways, forming a wireless sensor network (WSN) to detect diseases like mastitis. Our proposed susFL system incorporates a game-theoretic approach, called mechanism design, to select intelligent clients to optimize monitoring quality while minimizing energy use. This strategy ensures the system’s sustainability and resilience against various adversarial attacks, including data poisoning and privacy threats, that could disrupt FL operations. Our work in smart farm technologies sets a new standard by developing an animal monitoring system that is both energy-adaptive and resistant to attacks. Through extensive experiments, we demonstrate that our FL-based monitoring system significantly outperforms existing methods in prediction accuracy, operational efficiency, system reliability (i.e., mean time between failures or MTBF), and social welfare maximization by the mechanism designer. Our experimental results show that susFL significantly outperforms the state-of-the-art counterparts, including a 10% reduction in energy consumption, a 15% increase in social welfare, and a 34% rise in Mean Time Between Failures (MTBF) while maintaining the global model’s prediction accuracy.

This study presents a novel data preprocessing framework to enhance pig behavior analysis using machine learning techniques. We address the critical issue of data leakage in time series data, which can lead to overfitting and poor generalization in real-world applications. Our approach introduces two key innovations: a non-class-based windowing method and a chronological time sampling technique for train/test splitting. To evaluate these methods, we collected a comprehensive dataset spanning 100 hours of pig behavior over 24 days, using ear-tag sensors and video recordings to capture 12 distinct activities. We evaluate the effectiveness of our preprocessing methods using various machine learning and deep learning models on both time-domain and feature-domain datasets derived from this unique collection. Results demonstrate significant improvements in classification accuracy across all tested models, with increases of up to 15% compared to commonly used data preparation methods. The 2D Residual CNN achieved the highest accuracy of 95.6% in the time domain, while Random Forest performed best in the feature domain with 94.1% accuracy.

Accurate weight forecasting is essential for optimizing swine farming operations and enhancing animal welfare. This paper introduces a novel approach for pig weight forecasting, employing multi-input deep learning models that harness both depth images and statistical descriptors. The study conducts a comprehensive comparison of traditional machine learning (ML) models, deep learning (DL) models, hybrid ML and DL models, and multi-input models integrating both time-series data and image features. A meticulously curated dataset comprising time-series weight measurements and corresponding depth images of pigs forms the foundation of the study. Image descriptors such as length, width, depth, and volume were extracted from the depth images. The proposed multi-input models, employing architectures based on ResNet, XCeption, LSTM, and GRU layers, are meticulously trained and evaluated using this dataset. The performance evaluation is conducted using mean absolute error (MAE) and mean absolute percentage error (MAPE) metrics. The results underscore the superiority of the multi-input models over traditional ML, DL, and hybrid models. Notably, the best-performing model achieves a test MAE of 1.81 kg and a test MAPE of 5.56 %. This exceptional performance highlights the importance of leveraging both time-series data and image features for precise weight forecasting in pigs. These findings can hold significant implications for improving the efficiency and sustainability of swine farming practices, offering a pathway towards improved decision-making and animal management protocols.

Smart farms, as a way for better productivity and efficiency, have yet to be thoroughly studied for their service quality amid cyber threats. This work introduces a proactive security approach, Moving Target Defense (MTD), to the smart farm system to proactively address diverse cyber threats. Specifically, we develop an energy-aware MTD, termed eMTD, using port hopping for a sustainable smart farm network. Leveraging deep reinforcement learning (DRL), we identify the optimal MTD strategy capable of ensuring high monitoring quality of animal conditions and sufficient energy levels for solar-powered sensors on the farm. Our experiments demonstrate a significant improvement by approximately 15% in monitoring quality and remaining energy compared to other schemes.

While smart farm technologies significantly aid in reducing costs and boosting productivity for farmers, they often lack the necessary robustness against cyberattacks and adaptability to dynamic environmental changes. We propose a solar-powered sensor-based smart farm system to provide high monitoring quality while preserving sensor energy in the presence of adversarial attacks. In a smart farm system, solar-powered sensors are attached to animals (e.g., cows) to monitor their health under varying weather conditions to provide energy-adaptive and high-quality monitoring services. Further, a smart farm system should be robust against adversarial attacks aiming to disrupt monitoring quality. We use deep reinforcement learning (DRL) to identify the optimal policy for maximizing monitoring quality and prolonging the system’s lifetime while maintaining sufficient energy. We introduce transfer learning (TL) into the DRL process to achieve fast learning without experiencing a cold start problem in DRL. In addition, we develop an uncertainty-aware anomaly data detection method to filter out deceptive data caused by adversarial attacks. Via extensive comparative performance analysis conducted based on real datasets, we demonstrate the superior performance of the proposed TL-based DRL strategies over existing competitive counterparts in the system lifetime, the monitoring quality, the learning convergence time, and the energy consumption.

This paper aims to achieve ultra-low phase noise for a voltage-controlled oscillator (VCO) through the adoption of a dual-tank configuration. The tank, based on a 1:1 transformer, incorporates an impedance scaling mechanism to reduce the equivalent parallel resistance of the tank without compromising its quality factor. Additionally, the tank provides a passive voltage gain from the drain to the gate of the core transistors, resulting in a reduction of the phase noise of the core transistors and aiding the start-up of the VCO. The tank also provides impedance peaks at the fundamental and second harmonic frequencies, leading to a flattened voltage waveform for half an oscillation cycle at the core transistors’ drains, further reducing their phase noise contribution. The VCO is fabricated in 180-nm CMOS technology. The VCO, with a die size of 0.14 mm2, demonstrates a state-of-the-art phase noise of -157.2 dBc/Hz at an offset frequency of 10 MHz, with the center frequency of 5.08 GHz. The oscillator’s peak Figure-of-Merit is 193.2 dBc/Hz.

The proposed two-stage ensemble machine learning model aims to bridge the gap between energy harvesting and vibration sensing applications for lead zirconate titanate (PZT) and similar piezoceramic materials by enabling one device to perform both functions simultaneously. Two PZT cantilever configurations were tested: one without a tip mass for maximum linearity at low frequencies and one with a tip mass for maximum energy output. The highest absolute prediction error on the testing set is 19% and 7%, respectively. While the R2 score remained nearly 1, the PZT cantilever with the tip mass showed an 11% lower mean absolute error (MAE) and 38% lower mean squared error (MSE) compared to the PZT without, suggesting that PZT cantilevers in energy harvesting configurations can be used to predict acceleration with acceptable accuracy.

This paper presents a powerline energy harvesting circuit to power wireless sensor nodes for powerline safety monitoring. The magnetic harvester is a ring-shaped nano-crystalline magnetic core, which transforms the ac powerline current to ac voltage. The major building blocks of the circuit are a buck-boost converter operating in discontinuous conduction mode (DCM) and a microcontroller unit (MCU) for maximum power point tracking (MPPT). The MPPT algorithm based on the perturb and observe senses the current flowing into the load and adjusts the duty cycle of the buck-boost converter to match the source impedance. The magnetic core delivers 6.98 W to an optimal$200\ \Omega$resistor directly attached to the core under the powerline current of 30 A. The output power of the proposed circuit is 4.86 W with the optimal load resistance of$R_{L}=250\ \Omega$, resulting in the conversion efficiency of 70%.

This paper presents an investigation into practical considerations in the minimization of Age of Information (AoI) for the system architectures with and without updating feedback. To study the impact of the critical characteristics of the energy harvesters on the computing accuracy of the average AoI, an RF energy harvester with a half-wavelength patch antenna array along with a 3-stage voltage rectifier is designed and prototyped with the center frequency of 2.655 GHz. A cryptography algorithm is also implemented on a$\mu$-controller unit to imitate the behavior of a practical processing unit. The paper shows measurement results and discusses the impact of the non-idealities in the energy harvester on the average AoI of the system. It also shows that the nonlinear power conversion profile of the energy harvester can increase the average AoI to over 300% compared to an ideal and linear energy harvester.

This work proposes an energy-adaptive monitoring system for a smart farm using solar sensors attached to cows. The proposed system aims to achieve a high monitoring quality in the smart farm under fluctuating energy and cyber attacks disrupting the collection of sensed data from solar sensors, such as protocol noncompliance, false data injection, denial-of-service, and state manipulation. We adopt Subjective Logic, a belief model, to consider multidimensional uncertainty in sensed data. We employ deep reinforcement learning (DRL) for agents on gateways to collect high-quality sensed data from the solar sensors. The DRL agents aim to collect high-quality sensed data with low uncertainty and high freshness under fluctuating energy levels in solar sensors. We analyze the performance of the proposed energy-adaptive smart farm system in accumulated reward, monitoring error rate, and system overload. We conduct a comparative performance analysis of the uncertainty-aware DRL algorithms against their counterparts in choosing the number of sensed data to be updated to collect high-quality sensed data to achieve high resilience against attacks. Our results prove that multiagent proximal policy optimization (MAPPO) using the uncertainty maximization technique outperforms other counterparts, showing about 4% lower monitoring error rate and the system overload.

In this work, we propose an energy-adaptive moni-toring system for a solar sensor-based smart animal farm (e.g., cattle). The proposed smart farm system aims to maintain high-quality monitoring services by solar sensors with limited and fluctuating energy against a full set of cyberattack behaviors including false data injection, message dropping, or protocol non-compliance. We leverage Subjective Logic (SL) as the belief model to consider different types of uncertainties in opinions about sensed data. We develop two Deep Reinforcement Learning (D RL) schemes leveraging the design concept of uncertainty maximization in SL for DRL agents running on gateways to collect high-quality sensed data with low uncertainty and high freshness. We assess the performance of the proposed energy-adaptive smart farm system in terms of accumulated reward, monitoring error, system overload, and battery maintenance level. We compare the performance of the two DRL schemes developed (i.e., multi-agent deep Q-Iearning, MADQN, and multi-agent proximal policy optimization, MAPPO) with greedy and random baseline schemes in choosing the set of sensed data to be updated to collect high-quality sensed data to achieve resilience against attacks. Our experiments demonstrate that MAPPO with the uncertainty maximization technique outperforms its counterparts.

Edge intelligence can reduce power dissipation to enable power-hungry long-range wireless applications. This work applies edge intelligence to quantify the reduction in power dissipation. We designed a wireless sensor node with a LoRa radio and implemented a decision tree classifier, in situ, to classify behaviors of cattle. We estimate that employing edge intelligence on our wireless sensor node reduces its average power dissipation by up to a factor of 50, from 20.10 mW to 0.41 mW. We also observe that edge intelligence increases the link budget without significantly affecting average power dissipation.

This paper investigates direct and indirect learning methods to develop deep learning digital predistortion (DL-DPD) models and apply the models to improve the linearity of a power amplifier (PA). The two methods are applied to class-AB and class-$\mathrm{F}^{-1}$ PAs designed with gallium nitride (GaN) on silicon carbide (SiC) high electron mobility transistors (HEMTs). The simulation results show that both direct and indirect DL-DPD methods improve the linearity of the class-AB PA by about 12dB and the class-$\mathrm{F}^{-1}$ PA by 11 dB, while the indirect method offers marginally better performance. The paper shows the direct learning method leads to significant improvement of the DL-DPD method based over the memory polynomial. It also presents the advantages of a BiLSTM based on the neural network architecture to design direct/indirect DPDs. Finally, it demonstrates that the DL-DPD can improve the linearity of class-AB and class-$F^{-1}$ PAs without architectural changes.

This paper proposes an M-PSK (M-ary Phase Shift Keying) polar transmitter, which features low power dissipation, low design complexity, and compact core size. The key blocks of the proposed transmitter are a ring oscillator and a charge control unit, which dynamically set the amount of charge to draw from the output node of the oscillator. The charge drawn from the output node effectively shifts the phase of the output voltage waveform of the oscillator. It enables the transmitter to perform the phase shift keying by controlling of the amount of the charge to draw. The transmitter is laid out in TSMC 180 nm CMOS process technology. Post layout simulations show that the transmitter can achieve the data rate of 40 Mbps with the error vector magnitude (EVM) of 3.7% for 16-PSK signals.

This paper presents a temperature compensated variable gain phase shifter (VGPS), composed of an active phase shifter followed by a variable gain amplifier (VGA). A temperature sensor adjusts the biasing of the phase shifter block and suppresses temperature effects on its insertion phase. Further, a self-compensation mechanism compensates the gain reduction at the VGA stage. The circuit is designed and laid out in 0.15 μm GaN HEMT technology. Post layout simulation results show that the proposed VGPS achieves over 180 °C of the relative phase shift for the frequency range of 4.5 to 5 GHz over the temperature ranging from 25 °C to 250 °C. The gain of the VGPS can be controlled from 5 dB to 17 dB.

This paper presents a compact backscatter modulator tag operating at 1.76 GHz. The modulator is composed of a series combination of a variable resistor and a varactor. These components modulate the backscatter signal by adjusting the input impedance or input reflection coefficient. A gallium nitride (GaN) on silicon carbide (SiC) high electron mobility transistor (HEMT) is adopted to implement the variable resistor. The modulator can support a variety of modulation schemes without increasing the size and design complexity. The tag can be continuously powered through ambient RF energy in the 2.45 GHz frequency band. A differential rectifier harvests RF energy to power a microcontroller eliminating the need for a battery. Experimental results show that the modulator can support 16-QAM with an error vector magnitude (EVM) of 1.73%. The measured RF to DC power conversion efficiency (PCE) of the energy harvester is 57.1% at a received power of 1.7 dBm.

The proposed circuit aims to harvest energy from AC powerlines with a wide current ranging from 10 to 50 A. The proposed system includes a wake-up circuit and is capable of cold-start. A buck-boost converter operating in DCM is adopted for impedance matching, where the impedance is rather independent of the operation conditions. So, the proposed system can be applicable to various types of wireless sensor nodes with different internal impedances. Experimental results show that the proposed system achieves an efficiency of 80.6% under the powerline current of 50 A.

This article presents a high temperature model for gallium nitride (GaN) high electron mobility transistor (HEMT) on silicon carbide (SiC). The proposed model for the channel resistance Rds is based on an empirical nonlinear model. The model is applied to design a resistive mixer of a high temperature transceiver for downhole communications through a systematic approach and estimate the performance of the mixer. The proposed model matches well with measurement results of the mixer and accurately estimates its performance at temperatures up to 250 °C. The model is also applied to obtain the optimal gate bias voltage of the mixer for a given temperature. The optimal bias voltage scheme reduces the conversion loss of the mixer by a factor of 8.4 dB at 250 °C under the local oscillator power of -10 dBm.

A two-mode buck converter to accommodate both light and heavy load is presented in this paper. The converter operates in the heavy-buck mode optimized for heavy load and the baby-buck mode optimized for light load. The mode selector selects an appropriate mode based on the load current. The converter adopts the ripple-based constant on-time V2control. The circuit is designed in CMOS 0.25 μm CMOS technology. Measurement results indicate it achieves 70% to 80.6% efficiency for the load power ranging from 12 mW to 840 mW.

This paper presents an energy harvesting circuit for indoor light. The main design objective of the proposed circuit is high adaptability to various types of photovoltaic (PV) cells and coverage of a large range of PV voltages. A dual-input dual-output buck-boost running in discontinuous conduction mode (DCM) with pulse skipping modulation is adopted for the purpose. It proposes the fractional open-circuit voltage (FOCV) scheme with an adaptive fraction for maximum power point tracking (MPPT). The optimal fraction is obtained through the perturb & observe (P&O) scheme, which leads the proposed MPPT method adaptable to different types of PV cells. The circuits are designed in 0.18 μm BCDMOS process, and post-layout simulations verify correct operation of the proposed circuit.

The proposed circuit aims to harvest energy from body heat, in which the thermal gradient is only a few degrees. The boost converter operating in a burst mode offers a high conversion ratio while minimizing power loss. Maximum power point tracking based on the fractional open circuit voltage method ensures that the proposed circuit can be applied for a variety of thermoelectric generators (TEGs) and TEG setups. The proposed circuit is designed and laid out in CMOS 0.25 μm technology. Post layout simulation results indicate the converter is able to boost input voltages as low as 50 mV to the regulated output of 3 V, while achieving peak efficiency of 81%.

Electric vehicles require monitoring of car batteries. Wireless sensing is desirable to eliminate connecting wires, resulting in low installation and maintenance cost. This paper presents a low-power wireless sensor node and an interface circuit to monitor the battery pack of an electric vehicle. To save power, the proposed sensor node adopts the wake-up/sleep mode and reduces the transmission time through compaction of the data to transmit. The wireless sensor node is prototyped with a Texas Instruments low power microcontroller CC1310, where CC1310 embeds a variant of Zigbee radio and a 12-bit analog-to-digital converter. The prototype monitors the voltage and temperature of nine battery cells and the battery pack current. The measured power dissipation of the prototype is, on average, 1.2 mW. Considering the power dissipation of the microcontroller is 22 mw during transmission, the proposed method reduces the power substantially.

This paper presents an energy harvesting circuit for road speed bumps, in which energy is generated from passing over vehicles. As a speed bump energy harvester is mostly idle and generates energy intermittently for a short period, a major design issue is reduction of static power dissipation during the idle time. To address the problem, the proposed circuit adopts sleep mode. A speed bump energy harvester based on a piezoelectric cantilever translates kinetic energy generated by a passing over vehicle into electrical energy. Upon detection of the voltage generated by the piezoelectric cantilever, the proposed circuit wakes up the converter and extracts maximum power from the piezoelectric cantilever through impedance matching. When the piezoelectric cantilever does not generate voltage, i.e., a vehicle is not passing over the speed bump, the circuit shuts down major power hungry blocks to reduce the static power dissipation. The proposed circuit is designed in a 0.18 μm CMOS technology. Simulation results indicate that the typical static power dissipation of the proposed circuit is only 443 pW for the vehicle speed of 20 km/h, while the power dissipation of the circuit without sleep mode is 16.3 μV, an increase by a factor of 36,800 times.

This paper presents a multi-source energy harvesting system for vibration, thermal, and solar energy from automobiles, which aims to power a micro controller (MCU) for cryptography. Each building block adopts a maximum power extraction scheme to match the unique characteristic of the energy source. Resistive impedance matching with a buck-boost converter is adopted for vibration and thermal energy harvesting, and maximum power point tracking for solar energy harvesting. The proposed system provides two regulated voltages, 3.3 V and 5 V, to power an MCU. An energy level indicator indicates the current energy level stored in the storage device. The MCU processes a cryptography algorithm accordingly based on the current energy level. The system is able to cold start, i.e., even if the storage device is drained completely, it can start.

This paper presents a circuit for vibration energy harvesting from freight railcars, and it aims to power wireless sensor nodes (WSNs). An electromagnetic generator (EMG) converts vibration energy of a fright railcar into electrical energy. The proposed circuit adopts impedance matching to extract maximum power from the EMG and a wake-up circuit to save power when the fright railcar is not moving. A buck-boost converter running in discontinuous conduction mode is used for impedance matching. When the railcar is in motion, the wake-up circuit senses the EMG voltage and activates the buck-boost converter. Otherwise, the converter is deactivated to save power. The proposed circuit generates two regulated output voltages, 1.8 V and 3.3 V, to power WSNs. It is prototyped with discrete components. Experimental results show that the EMG attached on a freight railcar generates 7.07 V rms and has the source impedance of 300 Ω. The proposed circuit harvests peak power of 28.4 mW delivered to the load and achieves the efficiency of 67.6%.

This paper presents a system for vibration and thermal energy harvesting from automobiles, and it intends to power wireless sensor nodes. Two main features of the proposed circuit are impedance matching to extract maximum power and wake-up to incorporate sleep mode. Two separate buck-boost converters in discontinuous conduction mode are used for impedance matching. A wake-up circuit senses the vibration energy generated by a piezoelectric cantilever (PZT). When a car is turned off, the wake-up circuit deactivates the two converters, and the entire circuit goes into sleep mode to save power. The proposed circuit charges a capacitor to power a wireless sensor node, and is able to cold start. The proposed circuit is prototyped with discrete components. Experimental results show that the proposed system harvests peak power of 3.4 mW and these results also demonstrate that a wireless sensor node can be powered by the proposed system.

The decay of easily accessible reserves pushes the oil and gas industry to explore deeper wells, where the ambient temperature often exceeds 210 °C. The need for high temperature operation, combined with real-time data logging, results in a growing demand for robust, high temperature RF circuits. This paper presents a high temperature IF variable gain amplifier (VGA) for downhole communications, which is capable of operating at 230 °C. The proposed VGA is prototyped using GaN on SiC HEMT technology. Measured results at 230 °C show that the VGA has a peak gain of 27 dB at the center frequency of 97.5 MHz, and a dynamic range of 29.4 dB. The input P1dB compression at the peak gain is -11.57 dBm at 230 °C, and -3.63 dBm at 25 °C. The input and output return losses are above 12 dB across the entire temperature range from 25 °C to 230 °C. The maximum power gain and dynamic range drop by 1 dB and 4.7 dB, respectively, at 230 °C. The maximum power dissipation of the VGA is 176 mW under the peak gain at 230 °C.

This paper presents a high temperature voltage-controlled oscillator (VCO) for downhole communications. The proposed VCO adopts the common-source Colpitts oscillator configuration. The VCO is prototyped using 0.25 μm GaN RF transistors due to the high junction temperature and high unity gain frequency. Two GaN varactors are used to achieve the tuning frequency range of 40 MHz up to 230 °C. The measurements at 230 °C show that the VCO has an output power of 17.5 dBm with ±0.5 dB variations over the tuning range from 320.8 to 360.2 MHz. The measured phase noise is -121 dBc/Hz at 100 kHz offset from 343.3 MHz carrier. The maximum power consumption of the VCO is 122.5 mW.

The proposed circuit intends to harvest kinetic energy from electromagnetic generators. An AC-DC boost rectifier running in boundary conduction mode (BCM) performs resistive input matching, while reducing the converter power loss. The boost rectifier also merges a rectifier and a boost converter to reduce power loss for rectification. It also utilizes the internal inductance of the EMG to reduce the off-chip inductor size. An optional buck converter regulates the output voltage to 5 V to power devices through USB ports. The circuit is designed and fabricated in BiCMOS 0.18 μm technology.

As the oil industry continues to drill deeper to reach new wells, electronics are required to operate at extreme pressures and temperatures. Coupled with substantial real-time data targets, the need for robust high speed electronics is quickly on the rise. This paper presents a high temperature wideband low noise amplifier (LNA) with zero temperature coefficient maximum available gain (ZTCMAG) biasing for a downhole communication system. The proposed LNA is designed and prototyped using 0.25 μm GaN on SiC RF transistor technology, which is chosen due to the high junction temperature capability. Measurements show that the proposed LNA can operate reliably up to an ambient temperature of 230 C with a minimum noise figure (NF) of 2.0 dB, average gain of 16.1 dB, and input P1dB of 4.0 dBm from 230.5-285.5 MHz. The maximum variation with temperature from 25°C to 230°C is 1.53 dB for NF and 0.65 dB for gain.

As oil and gas industry drills deeper, temperatures of wells can exceed 210 °C. Conventional cooling and heat extraction techniques are impractical in the harsh environment, which necessitates reliable electronic systems to operate at high temperatures. This paper presents a high temperature RF downconversion mixer targeted for downhole communications. The proposed mixer is developed with a commercial Gallium Nitride (GaN) high electron mobility transistor (HEMT). The RF band for the mixer is 230-253 MHz and the IF frequency is 97.5 MHz. The mixer achieves the conversion gain of 6 dB at LO power of -10 dBm at temperature 250 °C, and the input P1dB compression point is -7 dBm. It dissipates 50 mW under 5 V supply. The proposed mixer achieves a relatively high conversion gain and good linearity at temperature of 250 °C.

As the circuit complexity increases, the number of internal nodes increases proportionally, and individual internal nodes are less accessible due to the limited number of available I/O pins. To address the problem, we proposed power line communications (PLCs) at the IC level, specifically the dual use of power pins and power distribution networks for application/ observation of test data as well as delivery of power. A PLC receiver presented in this paper intends to demonstrate the proof of concept, specifically the transmission of data through power lines. The main design objective of the proposed PLC receiver is the robust operation under variations and droops of the supply voltage rather than high data speed. The PLC receiver is designed and fabricated in CMOS 0.18-μm technology under a supply voltage of 1.8 V. The measurement results show that the receiver can tolerate a voltage drop of up to 0.423 V for a data rate of 10 Mb/s. The power dissipation of the receiver is 3.26 mW under 1.8 V supply, and the core area of the receiver is 74.9μm × 72.2 μm.

This paper presents a solar energy harvesting (EH) system to power a portable compact LED lamp, which can be charged during daytime and used to light during night time. The solar lamp consists of three PV panels, an EH and power management circuit, three NiMH rechargeable batteries, and an LED. A commercial off-the-shelf chip TI BQ25504 is used to prototype the EH and power management circuit for the proposed system. Experimental results show that the proposed PV system can harvest solar energy both in indoor and outdoor environments. The peak net power harvested by the proposed system is about 380 mW on a sunny day, 250 mW on a partly cloudy day, and 30 mW on a cloudy day.

In this paper, we present a system to estimate the health of a lead-acid car battery and warn the driver of upcoming battery failure in the near future. Most existing lead-acid battery state of health (SOH) estimation systems measure the battery impedance by sensing the voltage and current of a battery. However, current sensing is costly for parts and/or labor. A method to estimate SOH by sensing the battery voltage during a cranking event was proposed. Our system intends to improve a previous method. It measures the battery voltage during a cranking event, processes critical voltage points to estimate the SOH of the battery, and warns the driver of a potential upcoming failure.

This paper presents a self-powered rectifier for piezoelectric energy harvesting applications, and the key idea of the proposed system is to reset the transducer capacitor at optimal instants to maximize the extracted power. The proposed rectifier consists of two switches and two active diodes. The switches discharge the transducer capacitor at optimal instants two times for every cycle. The active diodes are based on op-amps with a preset dc offset, which reduces the voltage drop and the leakage current and avoids instability. In addition, the controller for the proposed rectifier is simple to reduce the circuit complexity and the power dissipation. The proposed rectifier was designed and fabricated in 0.18-μm CMOS technology. Measured results indicate that it achieves power efficiency of 91.2%, and the amount of power extracted by the proposed rectifier is 3.5 times larger when compared with the conventional rectifiers. The proposed rectifier does not require any off chip components to enable a full chip integration, and the die area of the proposed circuit is 0.08 × 0.20 mm2.

A 100 Gb/s CMOS transimpedance amplifier (TIA) for high speed optical communication receivers is presented in this paper. The TIA is based on a differential architecture and composed of a regulated cascode block and a differential amplifier with active feedback. It adopts peaking inductors and a capacitive degeneration scheme to increase the bandwidth. The TIA is designed and laid out in CMOS 65 nm CMOS technology. Post layout simulation results show that the TIA achieves 70 GHz bandwidth, 40 dBO transimpedance gain, ±4.36 ps of the group delay variation, and 31 pA/√Hz of the input referred noise current, and it dissipates 24 mW under 1.2V supply. The proposed TIA increases the bandwidth by more than two times when compared with other existing CMOS TIAs, while achieving comparable performance in other performance metrics.

This paper presents the design of a wearable energy harvesting jacket, which harvests energy from solar and body heat in the outdoor environment. The energy harvesting system consists of 16 photovoltaic (PV) cells, 12 thermoelectric generators (TEGs), and five power management chips, and it charges two AAA NiMH batteries in series. The 16 PV cells are partitioned into four zones (chest, back, right and left shoulders), where PV cells in the same zone are roughly subject to the same irradiation level. All the PV cells in the same zone are controlled to operate at nearly the same maximum power point. Six TEGs are connected in series to increase the output voltage, and two sets of those six TEGs are controlled by the same power management circuit. The average power harvested by the solar system ranges between 475 mW to 500 mW on a sunny day. The power generated by TEGs lies in μW range due to the low temperature gradient available within the jacket. The prototype illustrates the proposed solar energy harvesting system with partition of cells into different zones is simple, yet effective.

In this paper a novel temperature compensated current reference with modified PMOS cascode architecture is presented. Using PMOS transistors and substituting the typical current source resistor with a diode connected NMOS transistor, better temperature compensation is achieved avoiding the use of large valued resistors. This architecture, designed in the IBM 0.18 μm CMOS 7RF SOI technology, achieves a 16.5 ppm/°C temperature coefficient over range of 20 °C to 130 °C together with reduced power consumption, 38.7 μW at 1.5 V, and silicon area, 130μm2.

We proposed power line communication (PLC) through a microprocessor's power distribution network as a novel technique for communicating to any node inside a chip and demonstrated the suitability of Impulse Ultra-Wideband (UWB) communication. Applications of this scheme discussed in this paper exemplify the applicability of this scheme in future microprocessors. Further, data recovery block design is presented which detects short duration UWB impulses on its power line. The design has been done in IBM 0.13 um digital CMOS process and has been shown to consume 3.58 mW when operating from 1.2 V supply.

Harvesting small scale energy from otherwise wasted ambient energy sources has attracted immense research efforts for battery-powered wireless sensor networks for various applications such as structural health monitoring, industrial condition monitoring and healthcare. The power level which those applications may reach ranges from microwatts to milliwatts. Energy scavenged from ambient sources may be able to recharge or even eliminate the battery to power up those devices perpetually. Sources of energy for harvesting include, but are not limited, to light, thermal gradient, vibration, and radio frequency radiation. The fluctuation and intermittence of these ambient energy sources bring in challenging technical issues to make self-powered systems practical. Energy storage devices like rechargeable batteries or supercapacitors and efficient power management circuitry are indispensable to convert a dynamic environmental energy input into a stable power source. This presentation reviews principles of energy harvesting and practices for small scale energy harvesters and self-powered wireless sensor modules developed recently. Industry trends and possible research issues for further developments are discussed in order to give a technical insight into energy harvesting techniques and their applications.

This paper presents two different implementations of a low-power quadrature frequency source generator for medical implant communication service (MICS) applications. The first circuit uses a current-reuse VCO running at double the target frequency followed by a divide-by-two frequency divider. The circuit dissipates only 230 μW and achieves low phase noise of -127 dBc/Hz@1MHz. The second one adopts a parallel-coupling scheme to combine two current-reuse VCOs (P-QVCO). The circuit exhibits a moderate power consumption of 960 μW and achieves very low phase noise of -138 dBc/Hz@1MHz.

In this paper, we present a new coarse-grained reconfigurable architecture called FleXilicon for multimedia and wireless communications, which improves resource utilization and achieves a high degree of loop level parallelism (LLP). The proposed architecture mitigates major shortcomings with existing architectures through wider memory bandwidth, reconfigurable controller, and flexible word-length support. VLSI implementation of FleXilicon indicates that the proposed pipeline architecture can achieve a high speed operation up to 1 GHz using 65-nm SOI CMOS process with moderate silicon area. To estimate the performance of FleXilicon, we modeled the processor in SystemC and implemented five different types of applications commonly used in wireless communications and multimedia applications and compared its performance with an ARM processor and a TI digital signal processor. The simulation results indicate that FleXilicon reduces the number of clock cycles and increases the speed for all five applications. The reduction and speedup ratios are as large as two orders of magnitude for some applications.

This paper proposes a digital constant on-time control method for high switching frequency DC-DC buck converter, which eliminates the need for high resolution digital pulse-width modulator (DPWM) compared to constant frequency control. Both simulation and experimental results demonstrate performance improvement through the proposed off-time prediction method in terms of the oscillation amplitude of the output voltage.

With ever increasing complexity in new mechanical structures, as well as aging structures in operation, locating damage with structural health monitoring techniques is becoming increasingly important. Permanent deployment of structural health monitoring systems is limited by the availability of sensor technology. Previous efforts to miniaturize the hardware required for the impedance method of structural health monitoring resulted in prototypes reliant on a DAC for providing excitation to the structure of interest. In this paper, a new excitation technique using wideband digital signals is proposed to eliminate the power dissipated by a DAC in the system. An experiment is performed to compare performance of the proposed technique and previous excitation techniques. Results are presented and reveal no loss in damage detection performance while reducing the power dissipation.

In this paper, we propose a high speed adder which is adopted for our reconfigurable architecture called FleXilicon. To support sub-word parallelism, the FleXilicon architecture adopts 8-bit processing units as the atomic operation. Hence, high speed 8-bit adders are a key building block necessary for high performance. The proposed adder intends to speed up 8-bit adder operations. It is based on a conventional bypass adder scheme, but bypasses 2 bits on every adder bit stage rather than bypassing 4 bits on every four bit stages for conventional bypass adders. The proposed adder enables high speed operation for the FleXilicon and maximizes sub-word parallelism. The proposed adder is implemented with full custom design in CMOS 65 nm process. Simulation results show that the proposed adder is two times faster than existing adders for 8 bit additions.

This paper proposes a new reconfigurable architecture for multimedia and wireless communications. The proposed architecture addresses three critical design issues with the loop level parallelism, wide memory bandwidth, reconfigurable controller, and the support of flexible word-length. Several major functions of multimedia and wireless communication applications were implemented in SystemC to estimate the performance of the proposed architecture. Simulation results indicate that the proposed architecture performs far better than conventional processors

Design of a fully differential sixth order GHz range gm-C lowpass filter for DS-CDMA UWB (ultra wideband) transceivers is presented. The filter is composed of three identical cascaded biquad sections. The core of the filter is isolated from the source resistance by a folded cascode input stage. An outer negative feedback loop is used to lower the source resistance seen by the core of the filter and extend the bandwidth to a GHz range. Schemes for near orthogonal tuning of bandwidth and passband gain are described and verified. Peaking in the passband is maintained low to avoid distortion and reduced linearity. The proposed lowpass filter is designed in TSMC 0.18 /spl mu/m CMOS process. Post layout simulations show that the filter bandwidth is tunable over 600 MHz from 800 MHz to 1.4 GHz and the passband gain is tunable over 6 dB, while the passband peaking is maintained below 2 dB. The filter consumes 24.2 mW under supply voltage of 1.8 V.

We present a novel, quality-driven, architectural-level approach that trades-off the output quality to enable power-aware processing of multimedia streams. The error tolerance of multimedia data is exploited to selectively eliminate computation while maintaining a specified output quality. We construct relaxed, synthesized power macro-models for power-hungry units to predict the cycle-accurate power consumption of the input stream on the fly. The macro-models, together with an effective quality model, are integrated into a programmable architecture that allows both power savings and quality to be dynamically tuned with the available battery-life. In a case study, power monitors are integrated with functional units of the IDCT module of a MPEG-2 decoder. Experiments indicate that, for a moderate power monitor energy overhead of 5%, power savings of 72% in the functional units can be achieved resulting in an increase in battery life by 1.95 x.

Recent advances in dynamic power management (DPM) techniques have resulted in designs that support a rich set of power management options, both at the hardware and software levels. This has resulted in an explosion of the design space when analyzing the system-level tradeoffs of candidate DPM strategy designs. This paper proposes a design space exploration methodology based on a high-level, multi-layered modeling framework that facilitates rapid estimation of system-wide energy by providing the designer with a global view of the system. The framework is based on the extended finite state machine formalism and abstracts the component power modes, the operating environment and the DPM architecture into interacting, concurrent layers within a single, unified model. The modeling framework is coupled with a symbolic simulation engine to allow for rapid traversal of the large design space. We first illustrate how the proposed model can be constructed by making reasonable assumptions on the system and workload parameters, and then we show how analysis of various candidate strategies can be performed using this model. Our aim is to provide a high-level model that can be used to quickly assess the impact of various power management decisions on the system-wide energy. The framework can also be a formal basis for design of energy efficient power management systems.

This paper proposes a new signaling method for efficient scan design based on the dual use of on-chip power lines. The proposed signaling scheme intends to increase the channel capacity for the multiple parallel scan design, and we suggest adoption of the UWB (ultra wideband) and direct sequence-code division multiple access (DS-CDMA) communication technologies. Because of the wide bandwidth, a UWB signal can reduce its average power level practically to the noise level. The DS-CDMA further mitigates the noise and allows multiple scan inputs to share the interconnected power lines. We studied the feasibility of the proposed scheme through SPICE simulations and present the simulation results for a power distribution networks consisting of two metal layers.

Sleep deprivation attacks are a form of denial of service attack whereby an attacker renders a pervasive computing device inoperable by draining the battery more quickly than it would be drained under normal usage. We describe three main methods for an attacker to drain the battery: (1) service request power attacks, where repeated requests are made to the victim for services, typically over a network - even if the service is not provided the victim must expend energy deciding whether or not to honor the request; (2) benign power attacks, where the victim is made to execute a valid but energy-hungry task repeatedly, and (3) malignant power attacks, where the attacker modifies or creates an executable to make the system consume more energy than it would otherwise. Our initial results demonstrate the increased power consumption due to these attacks, which we believe are the first real examples of these attacks to appear in the literature. We also propose a power-secure architecture to thwart these power attacks by employing multi-level authentication and energy signatures.

Large wireless ad hoc and sensor networks impose tight constraints on cost and power dissipation, so nodes usually adopt a single transceiver approach. Since a single transceiver cannot assess the status of existing transmissions, it wastes valuable time and energy on handshaking packets and corrupted packets. To avoid such overhead, we propose a single transceiver approach based on ultra wideband (UWB) and a companion medium access control (MAC) layer based on busy tone multiple access (BTMA). BTMA reduces the time and energy spent on collisions as compared to handshaking protocols. It is well suited for ad hoc and sensor networks since it permits random, distributed medium access with no central point of failure. The single transceiver leverages the inherently low duty cycle of impulse-based UWB (I-UWB) to assess the status of a packet during its transmission. This paper describes the I-UWB system architecture, and simulations show that it effectively detects a busy signal without affecting data transmission.

This paper examines low power design techniques for discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) circuits applicable for low bit rate wireless video systems. The techniques include skipping DCT computation of low energy macroblocks, skipping IDCT computation of blocks with all coefficients equal to zero, using lower precision constant multipliers, gating the clock, and reducing transitions in the data path. The proposed DCT and IDCT circuits reduce power dissipation by, on average, 94% over baseline reference circuits.

The overall throughput of automatic test equipment (ATE) is affected by the download time of test data. An effective approach to the reduction of the download time is to compress test data before the download. A compression algorithm for test data should meet two requirements: lossless and simple decompression. In this paper, we propose a new test data compression method that aims to fully utilize the unique characteristics of test data compression. The key idea of the proposed method is to perform the Burrows-Wheeler transformation on the sequence of test patterns and then to apply run-length coding. Experimental results show that our compression method performs better than six other methods for compressing test data. The average compression ratio of the proposed method performed on 15 test data sets is 94.6, while that for the next best one, Gzip, is 65.0. The experimental results also show that our method indeed reduces the download time significantly, provided a dedicated hardware decompressor is employed.

We present the performance gain of dual smart antennas with adaptive combining at handsets for the 3GPP W-CDMA system. The adaptive algorithm based on the normalized least-mean-square (N-LMS) algorithm is employed, in which antenna weights are recursively obtained. To obtain the channel profile, we adopted the GBSB (geometrically based single bounce) elliptical and circular models. The simulation results show that the dual smart antenna system with adaptive combining performs better than a single antenna system and its performance gain is 3.3 dB for the GBSB elliptical model at BER of 5/spl times/10/sup -2/ and 5.5 dB for the GBSB circular model. The higher performance gain is achieved as the mobile velocity decreases.

This paper proposes a new method for block motion estimation based on center-biased hybrid search (CBHS) using plus search that employ a hybrid of a compact plus shaped search and a diamond search. It has only 5 search points for the best case and, on average, 6.6 search points. CBHS is about 34.3 times faster than the full-search algorithm. Hence, CBHS is consistently faster than the other suboptimal block-matching techniques. This paper compares the popular suboptimal block-matching technique with CBHS in which both the processing speed and the accuracy of motion compensation are tested over widely used H.263 test video sequences.

The focus of high-level built-in self-test (BIST) synthesis is register assignment, which involves system register assignment, BIST register assignment, and interconnection assignment. To reduce the complexity involved in the assignment process, existing high-level BIST synthesis methods decouple the three tasks and perform the tasks sequentially at the cost of global optimality. They also try to achieve only one objective: minimizing either area overhead or test time. Hence, those methods do not render exploration of large design space, which may result in a local optimum. In this paper, we propose a new approach to the BIST data path synthesis based on integer linear programming that performs the three register assignment tasks concurrently to yield optimal designs. In addition, our approach finds an optimal register assignment for each k-test session. Therefore, it offers a range of designs with different figures of merit in area and test time. Our experimental results show that our method successfully synthesizes a BIST circuit for every k-test session for all six circuits experimented. All the BIST circuits are better in area overhead than those generated by existing high-level BIST synthesis methods.

To improve the performance of geographically distributed cosimulation, we propose a concept called hierarchically grouped message. The concept improves cosimulation performance, preserving the cosimulation accuracy, by hierarchically grouping messages transferred between simulators in a short period of simulated time into a single physical message, thereby reducing the number of physical messages. Applying the concept to hybrid and optimistic cosimulation, we can reduce the number of rollbacks as well as the communication overhead accompanying the message transfer. Experimental results show the efficiency of the proposed method for practical examples in an internationally distributed cosimulation environment.

In this paper, we present a new method to the built-in selftestable data path synthesis based on integer linear programming (ILP). Our method performs system register assignment, built-in self-test (BIST) register assignment, and interconnection assignment concurrently to yield optimal designs. Our experimental results show that our method successfully synthesizes BIST circuits for all six circuits experimented. All the BIST circuits are better in area overhead than those generated by existing high-level BIST synthesis methods. Keywords high-level BIST synthesis, built-in self-test, BIST, ILP. 1.

A high-level built-in self-test (BIST) synthesis involves several tasks such as system register assignment, interconnection assignment, and BIST register assignment. Existing high-level BIST synthesis methods perform the tasks sequentially at the cost of global optimality. We proposed a new approach based on an integer linear programming (ILP). Our method achieves optimal solutions for most circuits in hardware overhead, but it takes a long processing time. In this paper, we present a heuristic method to address this problem. The heuristic partitions a given data flow graph into smaller regions based on control steps and applies the ILP for each region successively. Our heuristic reduces the processing time by several orders of magnitude, while the quality of the solution is slightly compromised. We present experimental results for six circuits and compare the results with other BIST synthesis methods.

Existing high-level BIST synthesis methods focus on one objective, minimizing either area overhead or test time. Hence, those methods do not render exploration of large design space, which may result in a local optimum. In this paper, we present a method which aims to address the problem. Our method tries to find an optimal register assignment for each k-test session. Therefore, it offers a range of designs to the designer with different figures of merit in area and test time. Experimental results show that our method performs better than or comparable to existing BIST synthesis systems.

The overall throughput of automatic test equipment (ATE) is sensitive to the download time of test data. An effective approach to the reduction of the download time is to compress test data before the download. The authors introduced a test data compression method which outperforms other methods for compressing test data. Our previous method was based on the Burrows-Wheeler transformation on the sequence of test patterns and run-length coding. In this paper, we present a new method, called COMPACT, which further improves our previous method. The key idea of COMPACT is to employ two data compression schemes, run-length coding for data with low activity and GZIP for data with high activity. COMPACT increases the compression ratio of test data, on average, by 1.9 times compared with our previous method.

The overall throughput of automatic test equipment (ATE) is sensitive to the download time of test data. An effective approach to the reduction of the download time is to compress test data before the download. A compression algorithm for test data should meet two requirements: lossless and simple decompression. In this paper we propose a new test data compression method that aims to fully utilize the unique characteristics of test data compression. The key idea of the proposed method is to perform the Burrows-Wheeler transformation on the sequence of test patterns, and then to apply run-length coding. The experimental results show that our compression method performs better than six other methods for compressing test data. The average compression ratio of the proposed method performed on five test data sets is 315, while that for the next best one, the LZW method, is 21.

HOPE is an efficient parallel fault simulator for synchronous sequential circuits that employs the parallel version of the single fault propagation technique. HOPE is based on an earlier fault simulator railed PROOFS, which employs several heuristics to efficiently drop faults and to avoid simulation of many inactive faults. In this paper, we propose three new techniques that substantially speed up parallel fault simulation: (1) reduction of faults simulated in parallel through mapping nonstem faults to stem faults, (2) a new fault injection method called functional fault injection, and (3) a combination of a static fault ordering method and a dynamic fault ordering method. Based on our experiments, our fault simulator, HOPE, which incorporates the proposed techniques, is about 1.6 times faster than PROOFS for 16 benchmark circuits.

Scan design can be viewed as scanning flip-flops, so that faults, otherwise aborted, are detected by meeting propagation and justification requirements. In this paper, we propose a new method which identifies justification and propagation requirements of aborted faults through combinational test generation and selects flip-flops to meet the requirements. Two procedures, optimal and heuristic, were considered in the process. We implemented the heuristic procedure in a program called BELLONA. BELLONA selects flip-flops progressively to lead to high fault efficiency. Our experimental results show that BELLONA achieves 100% fault efficiency for all circuits experimented with, on average, 19% of flip-flops selected.

VISION is an efficient parallel pattern fault simulator for synchronous sequential circuits. VISION is based on an earlier fault simulator called PARIS which was the first and a highly efficient parallel pattern fault simulator. In this paper, we propose four new heuristics which substantially speed up the parallel pattern fault simulation for synchronous sequential circuits. According to our experiments, our fault simulator, VISION, which incorporates the four heuristics, is about 1.6 times faster than PARIS for 16 benchmark circuits.

A highly successful parallel fault simulator, called PROOFS, for synchronous sequential circuits has been reported. The performance of PROOFS has been substantially improved in HOPE. In HOPE, a systematic way of screening out faults with short propagation zone is proposed. We propose several new techniques which further reduce the fault simulation time of HOPE. The new techniques are: functional fault injection, static fault ordering by fanout free regions and dynamic fault ordering of potentially detected faults. The three methods are incorporated into HOPE and called HOPE1.1. HOPE1.1 shows significant improvement in performance for all the benchmark circuits experimented as compared to HOPE. Experimental results show that HOPE1.1 is especially effective for large circuits. For s35932 which is the largest circuit experimented with, the number of events is reduced by 24%, and the CPU time by 53% compared to HOPE.

For the original article see ibid., vol.9, no.2, p.212-20 (1990). The commenters show a counterexample for the region extraction algorithm given in the above-mentioned work by F. Maamari and J. Rajski. A four-step region extraction algorithm was given to extract the exit lines of each stem. In steps 1 and 2, primary reconvergent gates (PRGs) and secondary reconvergent gates (SRGs) of the stem are identified. In steps 3 and 4, closing reconvergent gates (CRGs) and exit lines are computed. In step 2, the algorithm does not identify some SRGs which could be exit lines of the stem. As a result, the fault simulation may be incorrect for some faults. The commenters show this case using an example circuit.>

In this paper, we present a fast fault simulator, FSIM, for combinational circuits. FSIM is based on the parallel pattern single fault propagation (PPSFP) technique. The essential idea of FSIM is to simulate the circuit in the forward levelized order and to prune off unnecessary gates in the early stages. In this way, FSIM performs fault simulations only for the gates which are affected by 'the injected faults. Another key feature employed in FSIM is the use of multiple last-in first-out (L,IFO) stacks instead of the commonly used priority queue [9]. The propagation time of the mult,iple LIFO stacks is O(n) and that of the priority queue O(n log n), where n is the number of gates in the propagation zone of the fault under consideration. The two features achieve a substantial reduction of the processing time. Experimental results for ten benchmark circuits show that FSIM outperforms other competing PPSFP fault simulators, Moreover, the efficiency of FSIM is less dependent on the circuit structure than other fault simulators. Experimental results of FSIM for various packet sizes, i.e., the number of test patterns simulated at a time, are also presented.

In this paper, we describe a highly efficient automatic test pattern generator for stuck-open (SOP) faults, called SOPRANO, in CMOS combinational circuits. The key idea of SOPRANO is to convert a CMOS circuit into an equivalent gate level circuit and SOP faults into the equivalent stuck-at faults. Then SOPRANO derives test patterns for SOP faults using a gate level test pattern generator. Several techniques to reduce the test set size are introduced in SOPRANO. Experimental results performed on eight benchmark circuits show that SOPRANO achieves high SOP fault coverage and short processing time.

Experimental results show that the performance of the IEEE 802.2 and 802.5 protocols for a single token ring is severely degraded in an interconnected token ring network. Congestion at bridges in a network is the primary cause of the degradation of the performance. An approach is investigated in which a secondary transmission link is added to the backbone ring of a network to form a double-linked backbone ring network. The effective processing speed of bridges for this double-linked backbone ring network is double that of the original single-linked backbone ring network. The increased processing speed of the bridges enhances the performance of the network. Experimental results show that the proposed double-linked backbond ring network substantially enhances the utilization, throughput, and response time compared to the original network.>

An approach to the design of reconfigurable programmable logic arrays (RPLAs) is proposed in which diagnosis of faults and reconfiguration are performed simultaneously. The approach also takes advantage of a laser programmable interconnect to simplify the test circuitry and area overhead. The RPLA design presented makes it possible to diagnose and repair faults on bit lines, product lines, and output lines. The unrepairable area in the RPLA is kept to a minimum. Only one extra input is required for testability. A mapping process for masking out missing crosspoint faults is employed to further enhance the yield of PLAs. Experimental results on the area overhead and the yield of the proposed RPLAs are presented. The field of the proposed RPLAs is higher than that of the original PLAs.>

In this paper we investigate two aspects regarding the detection of stuck-open (SOP) faults using stuck-at test sets. First, we measure the SOP fault coverage of stuck-at test sets for various CMOS combinational circuits. The SOP fault coverage is compared with that of random pattern test sets. Second, we propose a method to improve the SOP fault coverage of stuck-at test sets by organizing the test sequence of stuck-at test sets. The performance of the proposed method is compared with that of a competing method. Experimental results show that the proposed method leads to smaller test sets and shorter processing time while achieving high SOP fault coverage.

A method is presented to design pseudoexhaustive testable (PET) PLAs (programmable logic arrays) that are suitable for BIST (built-in self-test) environments. The key idea of the design is to partition inputs and product lines into groups. During testing, a group of inputs and a group of product lines are selected and tested exhaustively. The proposed design leads to small test sizes and relatively small area overhead. Experimental results on 30 PLAs, comparing test set sizes and area overhead of different BIST PLA designs, are reported.>

Signature registers are commonly used to collect test responses in built-in self-testing (BIST). If the contents of signature registers can be used as test patterns, the overall testing time can be reduced due to improved testing parallelism. Moreover, the number of extra registers for implementing BIST could be reduced. Here, the characteristics of the patterns generated by signature registers are studied through analyses as well as experiments. It is shown that the patterns generated by signature registers are rarely repeated when the number of test patterns is relatively small compared to the number of possible patterns. It is also shown that the patterns generated are almost uniformly distributed. Therefore, signature registers can be used effectively as pseudorandom pattern generators. The practicality of using signature registers as pseudorandom pattern generators is investigated by fault simulation experiments using an example circuit.>

Programmable logic arrays (PLA's) are extensively used to realize area efficient combinational logic circuits. As the size of the PLA's increases, a cost-effective way to test them is to realize testable PLA's. In this paper a new approach to the design of testable PLA's is presented. The proposed method leads to testable PLA's with minimal area penalty and small number of tests that can be obtained as a by-product of the synthesis procedure, or can be directly obtained from the personality of the PLA's, thus simplifying the test derivation step. Results of an experiment involving 56 PLA's, to compare the test set sizes of differenit testable PLA designs (including the design proposed here) as well as the size of tests derived to detect single faults by algorithmic procedures are also reported.