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John C. Bean

dblp:52/1964 · DBLP profile ↗
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3ranked-venue papers
1as first author
0since 2021 · last 2007
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2Applied, interdisciplinary, general and emerging computing · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 100%
Computer networks
1 paper
Physical-layer communications · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › semiconductor devices
heterojunction bipolar transistor
0.011992
Silicon-based semiconductor heterostructures: column IV bandgap engineering · Proc. IEEE 1992
Integrated circuit design › semiconductor devices
semiconductor device design
0.011992
Silicon-based semiconductor heterostructures: column IV bandgap engineering · Proc. IEEE 1992
Physical-layer communications › optical communication
avalanche photodiode
0.011992
Silicon-based semiconductor heterostructures: column IV bandgap engineering · Proc. IEEE 1992
Physical-layer communications
optical communication
0.011992
Silicon-based semiconductor heterostructures: column IV bandgap engineering · Proc. IEEE 1992

Methods — techniques the papers use, named apart from their topics

molecular beam epitaxy · 0.0bandgap engineering · 0.0
YearPublicationVenuePosition
2007 Designing CMOS/molecular memories while considering device parameter variations
abstract
In recent years, many advances have been made in the development of molecular scale devices. Experimental data shows that these devices have potential for use in both memory and logic. This article describes the challenges faced in building crossbar array-based molecular memory and develops a methodology to optimize molecular scale architectures based on experimental device data taken at room temperature. In particular, issues in reading and writing such as memory using CMOS are discussed, and a solution is introduced for easily reading device conductivity states (typically characterized by very small currents). Additionally, a metric is derived to determine the voltages for writing to the crossbar array. The proposed memory design is also simulated with consideration to device parameter variations. Thus, the results presented here shed light on important design choices to be made at multiple abstraction levels, from devices to architectures. Simulation results, incorporating experimental device data, are presented using Cadence Spectre.
Garrett S. Rose, Yuxing Yao, James M. Tour, Adam C. Cabe, Nadine Gergel-Hackett, Nabanita Majumdar, John C. Bean, Lloyd R. Harriott, Mircea R. Stan
ACM J. Emerg. Technol. Comput. Syst.7
2006 Design approaches for hybrid CMOS/molecular memory based on experimental device data
abstract
In recent years many advances have been made in the development of molecular scale devices. Experimental data shows that these devices have potential for use in both memory and logic. This paper describes the challenges faced in building crossbar array based molecular memory, and develops a methodology to optimize molecular scale architectures based on experimental device data taken at room temperature. In particular, we discuss reading and writing such memory using CMOS and compiling a solution for easily reading device conductivity states (typically characterized by very small currents). Additionally, a metric is derived to determine the voltages for writing to the crossbar array. Simulation results, incorporating experimental device data, are presented using Cadence Spectre.
Garrett S. Rose, Adam C. Cabe, Nadine Gergel-Hackett, Nabanita Majumdar, Mircea R. Stan, John C. Bean, Lloyd R. Harriott, Yuxing Yao, James M. Tour
ACM Great Lakes Symposium on VLSI6
1992 Silicon-based semiconductor heterostructures: column IV bandgap engineering
abstract
The use of strained layer epitaxy to grow high-quality Ge/sub x/Si/sub 1-x//Si heterostructures and their application to a wide range of heterostructure devices are addressed. The author reviews the mechanisms of strained layer growth, the bandstructure of the resulting material, and its use in test devices, including superlattice avalanche photodiodes for fiber optic communication, intrasubband optical detectors and arrays operating in the 10-15 mu m wavelength range, mobility enhanced modulation-doped transistors, heterojunction bipolar transistors with cutoff frequencies of 75 GHz, and negative resistance devices based on resonant tunneling and real-space carrier transfer.>
John C. Bean
Proc. IEEE1