The M-input optimum likelihood-ratio receiver is generalized by considering the case of different signal amplitudes on the receiver primary input lines. Using the more general likelihood-ratio receiver as a reference, an equivalent optimum multilayer perceptron neural network (or neural receiver) is identified for detecting the presence of an M-dimensional target signal corrupted by bandlimited white Gaussian noise. Analytical results are supported by Monte Carlo simulation runs which indicate that the detection capability of the proposed neural receiver is not sensitive to the level of training or number of patterns in the training set.

A methodology and the supporting CAD (computer-aided design) tools are discussed for designing a digital system so that it can meet predefined testability requirements. The set of tools is called the Test Engineer's Assistant (TEA). The TEA system creates an environment in which the designer can perform performance assessment, functional design, and design for testability (DFT). TEA is developed to support automated DFT at the board and subsystem levels, to aid in an appropriate choice of BIT (built-in test) techniques at the board level that is supported at the subsystem and system levels, to indicate where to augment system function with predefined BIT modules to increase testability, and to assess the hardware costs of implementing DFT and BIT.>

The performance and cost of a modulo-3 residue code checker that has been attached to a pipelined serial multiplier to provide a concurrent self-test capability are considered. Analytical results are derived for error detection coverage and minimum error latency; these quantities are observed to be in agreement with simulation results obtained by using ISPS, a register-transfer language. The residue checker error detection coverage and minimum error latency are observed to be dependent on the statistical properties of the multiplier input operands. The checker and serial multiplier were implemented in 4- mu m NMOS, using a standard cell design. The residue code checker required approximately half of the total silicon area.>