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Jinling Dai

dblp:52/2523 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 2018
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 72% Hardware reliability and fault tolerance · 22% Integrated circuit design · 6%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware reliability and fault tolerance
fault injection
0.312018
Simulation-Based Diagnostic Model for Automatic Testability Analysis of Analog Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018
Electronic design automation › hardware verification and test
fault simulation
0.312018
Simulation-Based Diagnostic Model for Automatic Testability Analysis of Analog Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018
Electronic design automation
hardware verification and test
0.312018
Simulation-Based Diagnostic Model for Automatic Testability Analysis of Analog Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018
Electronic design automation › hardware verification and test
testability analysis
0.312018
Simulation-Based Diagnostic Model for Automatic Testability Analysis of Analog Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018
Integrated circuit design
analog and mixed-signal circuits
0.112018
Simulation-Based Diagnostic Model for Automatic Testability Analysis of Analog Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018
Electronic design automation › hardware verification and test › analog circuit testing
analog fault detection
0.112018
Simulation-Based Diagnostic Model for Automatic Testability Analysis of Analog Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018

Methods — techniques the papers use, named apart from their topics

sample compression · 0.3leave-one-out cross-validation · 0.3kernel density estimation · 0.3k-nearest neighbor · 0.3
YearPublicationVenuePosition
2018 Simulation-Based Diagnostic Model for Automatic Testability Analysis of Analog Circuits
abstract
A novel data-driven simulation-based diagnostic model is proposed to realize automatic and practical testability analysis (TA) of analog circuits. With this model and the corresponding methods, sufficient faults can be handily injected into the circuit under test and then be simulated to construct the sample data. Using these data, a kernel density estimation on K-nearest neighbors classification algorithm and its leave-one-out cross-validation method are studied to evaluate the testability metrics. To handle the possible high false alarm caused by the faults that have similar samples with the fault-free case, two strategies are carried out by ignoring the faults in the ambiguity groups or/and using the posterior weights to determine the final classification results. Furthermore, a sample compression approach is proposed to reduce the computational cost. Experimental results show that more accurate and reasonable TA and verification can be achieved by comparing with the traditional testability models and the state-of-the-art classification methods. And the diagnostic application against a real circuit based on the simulation data can also reach a satisfactory level.
Xiaofeng Tang, Aiqiang Xu, Jinling Dai
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.5
2017 On the Average Rate and Power Allocation of Uplink Multi-Antenna NOMA Systems
abstract
In this paper, we consider low-complexity design of multi-antenna uplink non-orthogonal multiple access (NOMA) system. There are 2N user equipments (UEs) distributed uniformly in a circle, where the N UEs nearer to the base station (BS) are called strong UEs and the other N farther UEs are called weak UEs. The BS decodes the strong UEs' signals by zero-forcing (ZF) detector first, and subtracts the strong UEs' signals. Then, the BS decodes the weak UEs' signals by ZF detector. For the proposed scheme we obtain the closed-form expressions of the average rate under three scenarios. In addition, a power allocation policy is proposed to reduce the interference between the UEs and maximize the average sum rate. Numerical results verify the analytical results and show that the average sum rate of the proposed NOMA scheme outperforms that of the orthogonal multiple access scheme employing time division multiple access.
Jinling Dai, Chenyang Yang 0001
VTC Fall1