Multiprocessing and multithreading increase frequencies of thread schedulings and context switches. Context switches can decrease the system throughput because they disturb locality of references and cause cache misses such as translation lookaside buffer (TLB), LI, and L2 misses. To reduce the overhead due to context switches, we focus on the advantage of threads which share the same memory address space (sibling threads). In switching sibling threads, the operating system (OS) does not have to switch their memory address spaces. Thus, we can omit a part of switching procedure and expect an efficient use of memory hierarchy. To utilize this advantage, we have proposed a context aware scheduler, which aggregates sibling threads. By using our scheduler, we can expect to reduce the switches of memory address spaces in executing multithreaded applications. Because switching memory address spaces results in TLB flushes on some kinds of processors, our scheduler can be effective in reducing TLB misses on such platforms. In this paper, we evaluate the effect of our context aware scheduler on reducing TLB misses. For this purpose, we run several multithreaded applications simultaneously with our context aware scheduler and measure the number of TLB misses. From these experiments, we conclude that our context aware scheduler is effective in reducing TLB misses and contributes to enhance the system throughput without imposing the degradation of throughput on any application.

Fine-grained multithreading based on a natural model, such as dataflow model, is promising in achieving high efficiency and high programming productivity. In this paper, we discuss operating system issues for fine-grained multithread programs. We are developing an operating system called CEFOS based on a dataflow based computation model. A program on CEFOS consists of zero-wait threads which run to completion without suspension once started. Firing control among such threads is performed in a dataflow manner along with continuation relations in the program. Target platforms include fuce processor, which is dedicated to fine-grained multithreading, and commodity processors such as Intel x86. In this paper, after introducing our basic model and our operating system model, we discuss implementation issues on fuce and commodity platforms. The evaluation results indicate that our approach on commodity platforms is effective in reducing overheads while our approach on a special architecture naturally exploit parallelism even in I/O handling.

We propose a reinforcement learning algorithm to train a cooperative network with both discrete and continuous output neurons based on the finding that discrete and continuous motorneurons coexist in the gill-withdrawal neural network of the sea mollusk, Aplysia. The network was trained to control an inverted pendulum. Simulation experiments showed that the two output neurons had distinct but cooperative roles: the discrete output neuron was essential for fast learning while the continuous output neuron was necessary for learning fine control. To achieve both fast learning and fine control, the shape of the sigmoid function in the continuous output neuron should be set before learning.