Recent trends in the semiconductor industry have resulted in an increasing demand for low power circuits. POSE is a step in providing the EDA community and academia with an environment and tool suite for automatic synthesis and optimization of low power circuits. POSE provides a unified framework for specifying and maintaining power relevant circuit information and means of estimating power consumption of a circuit using different load models. POSE also gives a set of options for making area-power trade-offs during logic optimization.

This paper shows that using don't cares computed for area optimization during local node minimization may result in an increase in the power consumption of other nodes in a Boolean network. It then presents techniques for computing a subset of observability and satisfiability don't care conditions that can be used freely to optimize the local function of nodes. The concept of minimal variable support is then used to optimize the local function of each node for minimum power using its power relevant don't care set, that is, to reimplement the local function using a modified support that has a lower switching activity. Empirical results on a set of benchmark circuits are presented and discussed.

Article Free Access Share on Logic extraction and factorization for low power Authors: Sasan Iman Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CAView Profile , Massoud Pedram Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CAView Profile Authors Info & Claims DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation ConferenceJanuary 1995 Pages 248–253https://doi.org/10.1145/217474.217537Published:01 January 1995Publication History 31citation304DownloadsMetricsTotal Citations31Total Downloads304Last 12 Months5Last 6 weeks4 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

Recent advances in Field-Programmable Gate Arrays (FPGA) and programmable interconnects have made it possible to build efficient hardware emulation engines. In addition, improvements in Computer-Aided Design (CAD) tools, mainly in synthesis tools, greatly simplify the design of large circuits. The RPM (Rapid Prototype Engine for Multiprocessors) Project leverages these two technological advances. Its goal is to develop a common hardware platform for the emulation of multiprocessor systems with different architectures.

We study the problem of two-level logic minimization for low power in static CMOS circuits. We start by defining Power Prime Implicants (PPIs) which identify the set of all implicants that are sufficient and necessary for obtaining a minimum power solution. We then provide an efficient algorithm for generating the set of all PPIs of a function. The set of all PPIs is then used in a minimum covering problem to find the best power solution. The feasibility of generating the set of all PPIs and the increased complexity of solving the minimum covering problem are analyzed by deriving an upper bound on the expected number of PPIs which shows it to be linearly proportional to the number of prime implicants of the function. The results of our experiments are then used to draw conclusions on the effectiveness of low power two-level logic minimization.

Abstract- This paper presents a placement-driven technology mapping procedure based on fuzzy delay curves. The fuzziness has been introduced to deal with the inherent vagueness in wiring loads (derived from a dynamically updated placement) and used by the mapper to calculate the signal arrival times. In the process we describe a number of fuzzy operations which are needed to generate the fuzzy delay curves and to select a minimum area mapping solution satisfying a set of timing constraints. This procedure has been implemented and the results are on average 1% and 26 % (5 % and 3%)better in terms of area and delay compared to a technology mapping procedure with zero (crisp) wire load values. 1