This paper describes a tunable transient filter (TTF) design for soft error rate reduction in combinational logic circuits. TTFs can be inserted into combinational circuits to suppress propagated single- event upsets (SEUs) before they can be captured in latches/flip- flops. TTFs are tuned by adjusting the maximum width of the propagated SEU that can be suppressed. TTFs require 6-14 transistors, making them an attractive cost-effective option to reduce the soft error rate in combinational circuits. A global optimization approach based on geometric programming that integrates TTF insertion with dual-VoD and gate sizing is described. Simulation results for the 70 nm process technology indicate that a 17-48X reduction in the soft error rate can be achieved with this approach.

A combined approach for implementing system level test compression and core test scheduling to reduce SoC test costs is proposed in this paper. A broadcast scan based test compression algorithm for parallel testing of cores with multiple scan chains is used to reduce the test data of the SoC. Unlike other test compression schemes, the proposed algorithm doesn't require specialized test generation or fault simulation and is applicable with intellectual property (IP) cores. The core testing schedule with compression enabled is decided using a generalized strip packing algorithm. The hardware architecture to implement the proposed scheme is very simple. By using the combined approach, the total test data volume and test application time of the SoC is reduced to a level comparable with the test data volume and test application time of the largest core in the SoC

This paper presents fully parallel domain decomposition (DO) techniques for efficient simulation of large-scale linear circuits such as power grids. DD techniques that use non-overlapping and overlapping partitioning of power grids are described in this paper. Simulation results show that with the proposed parallel DD framework, existing linear circuit simulators can be extended to handle large-scale power grids. Results for circuits with more than four million nodes indicate that parallel DD with LU factorization is most suitable for power grid simulation. However, for densely connected power grids, parallel DD with additive Schwarz preconditioning offers maximum scalability and best performance.

To address the productivity bottlenecks in power analysis and optimization of modern systems, we propose to treat power as asignal and leverage the rich set of signal processing techniques. We first investigate the power signal properties of digital systems and analyze their limitations. We then study signal processing techniques to detect temporal and structuralcorrelations of power signals. Finally, we employ these techniquesto accelerate the simulation of an architecture-level power simulator. Our experiments with the SPEC2000 benchmark suite show that it is possible to accelerate power simulation by 100X without introducing significant errors at various resolution levels.

This paper presents analysis methods for energy estimation in RC trees driven by time-varying voltage sources, e.g., buffers, time-varying power supplies, and resonant clock generators. An Elmore energy model that is the computational analog of the conventional Elmore delay model for RC trees is described. Simulation results indicate that the error in energy estimation is less than 2.5% in the worst-case in comparison to HSPICE simulations, with over a 1000X speed-up.

This paper presents domain decomposition (DD) technique for efficient simulation of large-scale linear circuits such as power distribution networks. Simulation results show that by integrating the proposed DD framework, existing linear circuit simulators can be extended to handle otherwise intractable systems

An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU robustness of a logic gate is developed. This model -- in posynomial form -- is integrated with performance and power constraints into an optimization framework based on geometric programming for design space exploration. Simulation results for design optimization using simultaneous dual- VDD and gate sizing techniques for the 70 nm process technology demonstrate the tradeoffs that can be achieved with this approach.

An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU robustness of a logic gate is developed. This model is integrated with area and performance constraints into an optimization framework based on geometric programming for design space exploration. Simulation results demonstrate the design tradeoffs that can be achieved with this approach.

A gate-level radiation hardening technique for cost-effective reduction of the soft error failure rate in combinational logic circuits is described. The key idea is to exploit the asymmetric logical masking probabilities of gates, hardening gates that have the lowest logical masking probability to achieve cost-effective tradeoffs between overhead and soft error failure rate reduction. The asymmetry in the logical masking probabilities at a gate is leveraged by decoupling the physical from the logical (Boolean) aspects of soft error susceptibility of the gate. Gates are hardened to single-event upsets (SEUs) with specified worst case characteristics in increasing order of their logical masking probability, thereby maximizing the reduction in the soft error failure rate for specified overhead costs (area, power, and delay). Gate sizing for radiation hardening uses a novel gate (transistor) sizing technique that is both efficient and accurate. A full set of experimental results for process technologies ranging from 180 to 70 nm demonstrates the cost-effective tradeoffs that can be achieved. On average, the proposed technique has a radiation hardening overhead of 38.3%, 27.1%, and 3.8% in area, power, and delay for worst case SEUs across the four process technologies.

A rational Arnoldi method for passivity-preserving model-order reduction (MOR) with implicit multi-point moment matching for systems with frequency-dependent interconnects is described. The structure H(s) = sE - A - K√f, which arises from frequency-dependent effects in high speed interconnects, is preserved by the proposed MOR technique. Moment matching using congruence transforms and based on two types of moments that are derivatives of the transfer function w.r.t s and √f is described. Simulation results show that the proposed approach can significantly reduce the complexity of systems with frequency-dependent elements, while retaining high accuracy in comparison to the original system in both the time and frequency domains.

A radiation hardening technique for combinational logic circuits is described. The key idea is to exploit the asymmetric logical masking probabilities of gates, hardening gates that have the lowest logical masking probability to achieve cost-effective tradeoffs between overhead and soft error failure rate reduction. The technique, which decouples the physical from the logical aspects of soft error susceptibility of a gate, uses a gate (transistor) sizing technique that is both efficient and accurate (in comparison to SPICE). A full set of experimental results demonstrate the cost-effective tradeoffs that can be achieved.

A novel technique to model resistive bridging defects in the presence of inductive and capacitive effects is described. It is well known that resistive bridges can degrade performance without resulting in logic errors-the focus of This work is on the analysis and computation of this extra switching delay caused by resistive bridging defects between interconnect lines. Through a series of transformations, a simple, highly accurate, and computationally efficient closed-form RLC model for resistive bridges between interconnect lines is developed. This single-stage RLC model can accommodate a resistive bridge at an arbitrary site between two interconnect lines. A full set of simulation results show that on average, the model is 25X faster and accurate to within 4% of the results obtained using a 20-stage distributed RLC interconnect model in SPICE.