Ambient-sensitive pharmaceutical products can be degraded if exposed to inappropriate temperature, humidity, light or movement conditions. Although most drugs are properly handled in hospitals, once they are dispensed to ambulatory patients, the prescribed environmental preserving conditions are not always met. The present work proposes a global design to support the proper drugs preservation once they are dispensed to the patient. The proposed solution consists of a monitoring network and a servers system. The former is composed by a sensor node attached to the medicament to collect the conservation parameters, and a gateway installed at the patients' home to periodically capture and analyze this data prior to forwarding them to the data server. The servers system processes this information to monitor, in real time, the drug conservation parameters. Whenever any preserving parameter is considered not acceptable, the system will automatically generate an alert to warn the patient and the hospital pharmacy practitioners. Moreover, blockchain technology is adopted to register key information, specifically to immutably record whenever an alert regarding the conservation conditions of the drugs is generated/deactivated. Furthermore, Elliptic Curve Cryptography signatures are introduced to verify the identity of gateways that originate the messages interchanged in the system. Finally, energy efficiency has been considered as a major issue in order to prolong the battery autonomy of the sensor nodes affixed to the dispensed drugs.

Edge artificial intelligence (AI) is receiving a tremendous amount of interest from the machine learning community due to the ever-increasing popularization of the Internet of Things (IoT). Unfortunately, the incorporation of AI characteristics to edge computing devices presents the drawbacks of being power and area hungry for typical deep learning techniques such as convolutional neural networks (CNNs). In this work, we propose a power-and-area efficient architecture based on the exploitation of the correlation phenomenon in stochastic computing (SC) systems. The proposed architecture solves the challenges that a CNN implementation with SC (SC-CNN) may present, such as the high resources used in binary-to-stochastic conversion, the inaccuracy produced by undesired correlation between signals, and the complexity of the stochastic maximum function implementation. To prove that our architecture meets the requirements of edge intelligence realization, we embed a fully parallel CNN in a single field-programmable gate array (FPGA) chip. The results obtained showed a better performance than traditional binary logic and other SC implementations. In addition, we performed a full VLSI synthesis of the proposed design, showing that it presents better overall characteristics than other recently published VLSI architectures.

In this work we propose a new methodology for neural network hardware implementation based on an efficient combination of Stochastic Computing and Morphological Neural Networks (MNN). The main reasons behind the use of morphological neurons instead of conventional ones are that activation functions are not necessary and that Stochastic Computing emerges as a natural and compact way to implement MNN. The proposed design methodology has been verified by implementing classical pattern recognition problems such as Fisher’s IRIS dataset or handwritten digit recognition problems. As a result, the proposed design is able to provide competitive accuracy results along with higher energy efficiency and hardware compactness than other alternatives.

Mobile systems and by extension Internet of Things (IoT) applications requests more and more Machine Learning functions, thus requiring a big computational power with a small power available. These demands have led to renewed interest in unconventional hardware computing methods capable of to implement complex functions in a simple way, with a very small power consumption. This work proposes a novel System-on-Chip (SoC) implementation of a Kohonen Map based on stochastic computing. In turn, to support this development, several stochastic block designs are presented as Winner-Take-All (WTA) similarity check and the squared Euclidian distance. The capabilities and performance of the proposed SoC solution is tested over a well-known classification task over the Fisher's Iris data set, archiving the same classification performance than the software. The proposed solution requests few hardware resources and low power, due to its inherent capacity to implement complex functions in a simple way. This enables to implement large self-learning classifiers based on Kohonen maps on tiny systems.

The development of power-efficient Machine Learning Hardware is of high importance to provide Artificial Intelligence (AI) characteristics to those devices operating at the Edge. Unfortunately, state-of-the-art data-driven AI techniques such as deep learning are too costly in terms of hardware and energy requirements for Edge Computing (EC) devices. Recently, Cellular Automata (CA) have been proposed as a feasible way to implement Reservoir Computing (RC) systems in which the automaton rule is fixed and the training is performed using a linear regression model. In this work we show that Reservoir Computing based on CA may arise as a promising AI alternative for devices operating at the edge due to its intrinsic simplicity. For this purpose, a new low-power CA-based reservoir hardware is proposed and implemented in a FPGA (known as ReCA circuitry). The use of Elementary Cellular Automata (ECA) is able to further simplify the RC structure to implement a power efficient AI system suitable to be implemented in EC applications. Experiments have been conducted on the well-known MNIST handwritten digits database, obtaining competitive results in terms of processing time, circuit area, power and inference accuracy.

Spiking neural networks (SNN) are able to emulate real neural behavior with high confidence due to their bio-inspired nature. Many designs have been proposed for the implementation of SNN in hardware, although the realization of high-density and biologically-inspired SNN is currently a complex challenge of high scientific and technical interest. In this work, we propose a compact digital design for the implementation of high-volume SNN that considers the intrinsic stochastic processes present in biological neurons and enables high-density hardware implementation. The proposed stochastic SNN model (SSNN) is compared with previous SSNN models, achieving a higher processing speed. We also show how the proposed model can be scaled to high-volume neural networks trained by using back propagation and applied to a pattern classification task. The proposed model achieves better results compared with other recently-published SNN models configured with unsupervised STDP learning.

In this work we present a methodology to design circuits emulating memristive behaviour. This methodology is based initially on a charge and flux description of the system, and the equations are decomposed into blocks that can be implemented using very simple CMOS topologies. As an example, we implement a simple memristor with long term memory, showing that the resulting system behaves as expected using either voltage ramps or pulses as the driving signals.

In this paper, a sequential test technique is proposed to test a RF front-end receiver. With this technique the test circuitry can be reused by the receiver building blocks.The method is suitable to be fully integrated on-chip. Moreover, the test area overhead has been kept low by using the receiver LO in the test circuitry. Therefore the test circuitry required to generate the test stimuli are an IF generator and an auxiliary mixer. The above technique has been combined with a test strategy based on the estimation of selected performance parameters of the receiver building blocks. These estimations are done by using easily measurable test observables as DC supply current consumption. RMS estimation errors for the gain and the 1dB compression point of the LNA and the down converter in the receiver chain are all below 2%.

A BIC sensor for mixed signal ICs and its application to a simple A/D flash converter is presented. OBT for analog parts and I/sub DDQ/ for digital ones is considered. High fault coverage for opens and bridges, and low impact in circuit performances are achieved.

In this work the need for specific ATPG targeting Gate Oxide Short (GOS) defects is highlighted. Many works have been done to develop ATPG for resistive shorts considering both external bridges between gates, and intra-gate shorts. We show with some examples that in some cases the detection of all detectable intra-gate bridging faults does not imply covering all detectable GOS defects in the circuit. A commercially available standard gate library is analyzed to demonstrate that this problem may appear in real applications. An ATPG tool oriented to detect GOS defects with I/sub DDQ/ testing is presented. ATPG experiments on a set of benchmark circuits show the efficiency of the proposed tool.

I/sub DDQ/ testing is a powerful strategy for detecting defects that do not alter the logic behavior of CMOS ICs. Such a technique is very effective especially in the detection of bridging defects although some opens can be also detected. However, an important set of open and parametric defects escape quiescent power supply current testing because they prevent current elevation. Extending the consumption current testing time, from the static period to the dynamic one (i.e. considering the transient current), defects not covered with I/sub DDQ/ can be detected. Simulations using an on-chip sensor show that this technique can reach a high coverage for defects preventing current and also for those raising the static power consumption.

An exhaustive classification of bridging faults between pairs of logic level circuit nodes and an I/sub DDQ/ testability analysis scheme for these faults are presented in this paper. The case of feedback bridging faults producing oscillations is considered in detail. The testability of such faults is verified through a set of experiments with specially implemented ASIC's.>