The authors present an algorithm for hierarchical test generation based on module-oriented decision making (MODEM). The algorithm deals with combinational logic modules and the traditional single-stuck-at model. Modules and faults are captured at the function as well as the gate level. The benefits of hierarchy are realized by introducing a generic module representation and the concepts of a dynamic netlist and a dynamic calculus. The authors present the key elements of MODEM: the framework and fault targeting strategy, the module characterization, and a notation and calculus for module-oriented decision making. They conclude with a high-level view of MODEM implementation and experimental results on a variety of hierarchical benchmarks.>

The authors have proposed and implemented a dynamic framework and a method for hierarchically generating test patterns from a hierarchical net list. They have shown consistent gains in CPU over the traditional gate-level implementation while maintaining identical levels of fault coverage. In generating and characterizing modules for a large and varied set of hierarchical benchmarks, the authors benefited considerably from the consistent representations that are available during synthesis from a high-level description or when modules are generated by a process of technology mapping into standard cells. The authors introduced the concept of a single generic module which is hierarchical; the traditional AND, OR, NAND, and NOR are included implicitly. They developed a module-oriented decision-making algorithm, MODEM, which entails a dynamic calculus and procedures such as implication, error propagation, line justification, and probabilistic testability measures for a single generic module. Without loss of generality they adapted the control flow and basic features of PODEM in the first implementation of MODEM.>

The authors present a scan-based testability system that is an integral part of the cell-based design system at Microelectronics Center of North Carolina. The basic system consists of five modules: a scan-based audit to verify compliance with scan-based rules, a testability assessment module that projects fault coverage before any patterns are applied, a fast fault simulator that grades random and user-supplied patterns, an algorithmic test-pattern generator that produces test for faults that resist detection with random patterns or declares them redundant, and a test-pattern compactor to further reduce the size of the test-pattern set. The system serves as a platform for research into hierarchical methods, redundancy identification and removal, automated test point insertion, improved random test pattern generation, fault simulation, and boundary scan.>