Design space exploration (DSE) through system-level simulation is essential for designing energy-efficient asynchronous neuromorphic hardware, which is increasingly promising in edge AI applications. However, there are significant mismatches between system-level predictions and gate-level simulations, resulting in low precision when predicting performance during the DSE process for asynchronous neuromorphic hardware. To address this issue, we put forward ANGraph, a graph neural network (GNN)-based performance prediction framework for asynchronous neuromorphic hardware. In the ANGraph framework, we transform the intermediate representation of systemlevel simulations into graphs, collect gate-level circuit simulation results to build benchmarks with over one million samples, and train a GNN model to predict hardware latency for asynchronous neuromorphic hardware. Additionally, we use a residual network (ResNet)-based method to predict the power consumption of asynchronous neuromorphic hardware. We evaluate these two models on additional datasets without extra training across different scales, process nodes, and traffic patterns of input data. Compared to the latency predictions from the state-of-the-art simulator, we improve the R -square score by 0.69 and reduce root mean square error (RMSE) by 76% on average across all datasets. We also achieve an R-square score of 0.98 and a mean absolute percentage error (MAPE) of 0.88% for the power consumption prediction task. The benchmarks and models are available at https://github.com/HuaGuaiGuai/ANGraph.

Asynchronous circuits become an attractive alternative to synchronous circuits owing to their potential benefits such as low power consumption, and no clock distribution problems. However, handshake control and relative timing analysis make designing asynchronous circuits a complex and error-prone task. Moreover, traditional electronic design automation (EDA) tools are tailored specifically for synchronous circuits, resulting in significant manual effort when designing asynchronous circuits. To address these issues, this paper proposes a desynchronization method based on Chisel, which converts synchronous circuits into bundled-data asynchronous ones automatically. For demonstration, an open-source synchronous RISC-V processor is desynchronized to an asynchronous one, and both are implemented on Zynq7020 FPGA. The experimental results illustrate that the power consumption of Clicks for handshaking in the desynchronized processor is only 33.3% of that of the global clocks in the synchronous one. Besides, with Clicks the power consumption of memory access is reduced by 80%. Compared with previous synchronous and asynchronous RISC-V processors, the asynchronous RISC-V processor achieves up to 8.4x and 1.5x dynamic power reductions respectively.

Image deblurring is a critical task in the field of image restoration, aiming to eliminate blurring artifacts. However, the challenge of addressing non-uniform blurring leads to an ill-posed problem, which limits the generalization performance of existing deblurring models. To solve the problem, we propose a framework SAM-Deblur, integrating prior knowledge from the Segment Anything Model (SAM) into the deblurring task for the first time. In particular, SAM-Deblur is divided into three stages. First, we preprocess the blurred images, obtain segment masks via SAM, and propose a mask dropout method for training to enhance model robustness. Then, to fully leverage the structural priors generated by SAM, we propose a Mask Average Pooling (MAP) unit specifically designed to average SAM-generated segmented areas, serving as a plug-and-play component which can be seamlessly integrated into existing deblurring networks. Finally, we feed the fused features generated by the MAP Unit into the deblurring model to obtain a sharp image. Experimental results on the RealBlurJ, ReloBlur, and REDS datasets reveal that incorporating our methods improves GoPro-trained NAFNet’s PSNR by 0.05, 0.96, and 7.03, respectively. Project page is available at GitHub HPLQAQ/SAM-Deblur.

Event-driven asynchronous neuromorphic hardware is emerging for edge computing with high energy efficiency. In order to obtain the architecture with the best hardware performance, we need to search both the numerical and non-numerical design space of asynchronous neuromorphic hardware. However, it is challenging to find an optimal hardware architecture from the non-numerical design space. To address this problem, we propose an asynchronous neuromorphic hardware architecture search (ANAS) method, which uses an evolutionary algorithm to optimize both the numerical and non-numerical design space. Besides, we introduce a configurable asynchronous neuromorphic hardware simulator (CanMore) to offer system-level modeling and performance estimation. Experimental results show that ANAS rivals the best human-designed architecture by 7 × EDP reduction, and offers 2.3 × EDP reduction than the methods that only optimize numerical design space.

Text-to-speech(TTS) has undergone remarkable improvements in performance, particularly with the advent of Denoising Diffusion Probabilistic Models (DDPMs).However, the perceived quality of audio depends not solely on its content, pitch, rhythm, and energy, but also on the physical environment.In this work, we propose ViT-TTS, the first visual TTS model with scalable diffusion transformers.ViT-TTS complement the phoneme sequence with the visual information to generate high-perceived audio, opening up new avenues for practical applications of AR and VR to allow a more immersive and realistic audio experience.To mitigate the data scarcity in learning visual acoustic information, we 1) introduce a selfsupervised learning framework to enhance both the visual-text encoder and denoiser decoder; 2) leverage the diffusion transformer scalable in terms of parameters and capacity to learn visual scene information.Experimental results demonstrate that ViT-TTS achieves new stateof-the-art results, outperforming cascaded systems and other baselines regardless of the visibility of the scene.With low-resource data (1h, 2h, 5h), ViT-TTS achieves comparative results with rich-resource baselines.1 2

Spiking Neural Networks (SNNs) offer a highly promising computing paradigm due to their biological plausibility, exceptional spatiotemporal information processing capability and low power consumption. As a temporal encoding scheme for SNNs, Time-To-First-Spike (TTFS) encodes information using the timing of a single spike, which allows spiking neurons to transmit information through sparse spike trains and results in lower power consumption and higher computational efficiency compared to traditional rate-based encoding counterparts. However, despite the advantages of the TTFS encoding scheme, the effective and efficient training of TTFS-based deep SNNs remains a significant and open research problem. In this work, we first examine the factors underlying the limitations of applying existing TTFS-based learning algorithms to deep SNNs. Specifically, we investigate issues related to over-sparsity of spikes and the complexity of finding the ‘causal set'. We then propose a simple yet efficient dynamic firing threshold (DFT) mechanism for spiking neurons to address these issues. Building upon the proposed DFT mechanism, we further introduce a novel direct training algorithm for TTFS-based deep SNNs, called DTA-TTFS. This method utilizes event-driven processing and spike timing to enable efficient learning of deep SNNs. The proposed training method was validated on the image classification task and experimental results clearly demonstrate that our proposed method achieves state-of-the-art accuracy in comparison to existing TTFS-based learning algorithms, while maintaining high levels of sparsity and energy efficiency on neuromorphic inference accelerator.

Anomaly detection (AD) aims to recognize abnormal inputs in testing data when only normal data are available during training. Most AD models perform well on specific datasets but are difficult to generalize to other tasks, especially on medical datasets with high heterogeneity. In this paper, we propose a student-teacher network with skip connections (Skip-ST) which is trained by a novel knowledge distillation paradigm called direct reverse knowledge distillation (DRKD) to realize AD. Skip-ST consists of a pretrained teacher encoder and a randomly initialized student decoder. The output of the teacher encoder's last layer is the input of the student decoder, which aims to recover the multi-scale representation extracted by the teacher encoder. We introduce skip connections between the teacher encoder and student decoder to prevent the student decoder from missing normal information of images at multi-scale. Experimental results show that Skip-ST achieves a 7.95% Area Under the Receiver Operating Characteristic (AUROC) improvement averagely on five challenging medical datasets, outperforming the state-of-the-art AD models. Our code is available at https://github.com/Arktis2022/Skip-TS.

Tooth-marks on tongues usually indicate the weakness of the spleen and stomach in traditional Chinese medicine (TCM). Therefore, tooth-marked tongue classification is important to health diagnosis in TCM clinic. Existing classification methods usually do not use the prior knowledge such as the location and width of tooth-marks, resulting in easily misclassification of unremarkable tongues. In this paper, we propose a prior regularization tooth-marked tongue method (PRTMTM), which makes full use of the prior knowledge of the position and width of tooth-marks. With PRTMTM, the original tongue image is first segmented to obtain the tongue edge position. Then, the prior mask map of tooth-marks is obtained by corroding the tongue from edge to interior according to the tooth-mark width. Finally, with a proposed regularization method, the tooth-marked tongues are classified accurately in the training process together with the prior mask map of tooth-marks. To verify our method comprehensively, we build twenty-five sub-training sets with different number of images and label distributions. Compared with state-of-the-art methods, the accuracy of our method is improved by 4.78% on average and 10.61% on maximum, the AUC by 0.04 on average and 0.07 on maximum, and the generated heatmap can highlight tooth-marked regions.

This paper presents a four-level pulse amplitude modulation (PAM-4) receiver that incorporates a continuous time linear equalizer, a variable gain amplifier, a phase interpolator-based clock and data recovery, and a 4-tap direct decision feedback equalizer (DFE) for moderate channel loss applications in wireline communication. A dynamic current-mode logic comparator (DCMLC) is proposed and employed in the DFE. The DCMLC, which adopts dynamic logic, breaks the trade-off between the bandwidth and the clock to Q delay in the traditional current-mode logic comparator (CMLC). Compared with the traditional CMLC, the DCMLC reduces the clock to Q delay by 36%, which allows the implementation of a 4-tap direct DFE. Moreover, the first tap feedback signals are directly tapped from the output of the DCMLC, allowing the first tap feedback current to initiate 0.5UI before the decision clock. The PAM-4 receiver prototype is fabricated in a 65nm CMOS process. At a data rate of 56-Gbps, it can compensate for up to 20.17dB loss and achieve a bit error rate$< 1\text{E}$-10 with a power efficiency of 4.75 pJ/bit.

In this paper, we implement a single-spike spiking neural network (SNN) accelerator on field programmable gate array (FPGA) with 512 hidden neurons. A single-spike spiking integrate-and-fire neural model is adopted, which emits only one spike during classification, and adder instead of multiplier is used to integrate input spikes in its implementation, consuming fewer power and area compared with other models. Different level sparse connection is adopted to reduce up to 75% weight memory with 0.016% overhead for storing connections. The SNN accelerator is verified by MNIST handwriting dataset with Xilinx VC707 FPGA. Results show that the single-spike SNN accelerator reached 96% accuracy, 2.8us classification latency and 1.13pJ/classiflcation energy efficiency with MNIST dataset.

The “event-driven” feature of asynchronous circuits enables the circuits to work when and where needed, making it a good alternative to design low-power circuits. However, asynchronous circuits are not widely adopted as a consequence of the lack of support by conventional EDA tools. In this article, we propose a novel design flow to implement the Click-based asynchronous bundled-data circuits efficiently down to mask layout with conventional EDA tools. To ensure timing correctness, we put forward an adaptive delay matching (ADM) method and perform accurate static timing analysis for the circuits. Compared with other asynchronous toolsets, the proposed design flow is more efficient and convenient to implement asynchronous circuits. An asynchronous convolution neural network accelerator is implemented in TSMC 180- and 65-nm CMOS process, respectively, to verify the proposed design flow. The silicon test results show that the asynchronous acceleratorhas 30% less power in the computing array than the synchronous one in the TSMC 65-nm CMOS process, and the energy efficiency of the asynchronous and synchronous accelerators are 1.539 TOPS/W and 1.37 TOPS/W, respectively. The energy efficiency of the asynchronous accelerator in the TSMC 180-nm CMOS process is 133 GOPS/W.

We have implemented an asynchronous mesh network. This paper describes our innovative design using a Click controller. Compared to designs that use other asynchronous circuit families with C-elements and four-phase bundled data, our two-phase Click-based Bounded Bundled Data design is faster, but introduces phase skews when handling concurrent traffic at a single node. Instead of eliminating the phase skews, we use them as computation slots. Our network uses a novel asynchronous arbiter with a queue that can accept data from both the four cardinal directions as well as from a local source, five directions in all. We have implemented our network design in 1 × 1, 2 × 2 and 4 × 4 sizes, larger network could be implemented easier since the isomorphism and modularity of the routing nodes. Our experiments show that an initial data item passes through a node in 157ns v.s. 81ns for non-delay-branch and delay-branch designs separately. Following items take about 65% as long. But for a network, the average latency of a node keeps almost same for different paths. We believe that with the non-delay-branch designs, our asynchronous mesh network could offer 10.1M routes per second for a 1 × 1 network and 5.33M routes per second for 2 × 2 or 5.06M for 4 × 4 networks, and work at the rate of 17.3M, 10.1M and 11.7M with the enhanced delay-branch way. For both cases, its latency is approximately linear with scale.

The success of the Unicondylar Knee Arthroplasty (UKA) surgery generally depends on whether the implantation of the single compartment knee prosthesis is appropriate. The trajectory of the femoral prosthesis relative to the gasket is an important factor in judging an appropriate implantation. In this paper we propose an UKA trajectory measurement system which includes the pressure sensors array, the data processing part and transceivers. The data is transmitted wirelessly and displayed on the screen in real-time. The algorithm for determining the maximum pressure point and trajectory fitting is put forward, in which a pressure distribution model with distance as the weight is established. According to this model, the number of the sensors used to calculate the maximum pressure is reduced significantly and the initial solution of the maximum point of pressure is obtained. The surrounding pressure sensors are then used to verify and solve the exact solution of the maximum point of pressure with the basic idea of machine learning. Finally, the improved least squares method is used to fit the trajectory of the maximum points of pressure. From the simulation results, we can find that the computational complexity of the algorithm is reduced and the calculation speed is improved compared with that based on finite element analysis or cubic spline interpolation, which meets the real-time requirement. Moreover, the algorithm in this system is easily to be realized in hardware in future work.

This paper presents a high-frequency pulse stimulation (HFPS) output stage of neuro-stimulator with extended average output current range and high power efficiency. The output stage features two parallel buck-boost converters without any filter capacitor at the output node. Compared with HFPS output stage with only one converter, the proposed circuit doubles the maximum average current by staggering the output of two converters. Compared with traditional voltage mode stimulation (VMS), HFPS improves the power efficiency by discharging the inductor current through the tissue load directly, rather than through a filter capacitor with constant voltage. Besides, the control circuit for the proposed HFPS is much simpler than that of traditional VMS converter, which reduces the current consumption significantly and thus improves the efficiency. Test results confirm that with staggered output of two parallel converters, the maximum average current is doubled. The maximum energy efficiency of the proposed HFPS is 76.4%.

To improve the accuracy of implant placement in Total Hip Replacement (THR) surgeries, this paper proposes a computer-aided visual system for THR which is composed of a customized acetabular cup, a multi-sensor femoral head trial and a computer for data processing and display. The customized trial is of the same size as the real prosthesis. An image sensor, a gyroscope and an e-compass (including an accelerometer and a magnetometer) are adopted in the femoral head trial. Reference patterns are designed and printed on the internal surface of the cup, whose images are taken by the image sensor for estimation of relative pose and position between the femoral head trial and the acetabulum cup. Two methods of pose estimation are adopted in this system: one based on images and the other based on motion data from gyroscope and e-compass. The efficient perspective-n-point (EPNP) algorithm is used in the image-based pose estimation and achieves a rotation relative error of less than 8% and a translation relative error of less than 10%. The complementary algorithm is adopted in the motion-based pose estimation to smooth the results. Experimental results verified the proposed system.

This paper presents a wirelessly monitoring system for Total Hip Replacement (THR) surgery. This system aims to measure and display the attitude and position of femoral head of prosthetic implant during the surgery. The system consists of two parts: the Sensors Array Measuring System (SAMS) and the display part. The SAMS is composed of a sensors array, signal conditioning circuits, a low power Micro Control Unit (MCU), and a low-power transceiver. The SAMS is designed to measure the contact distribution of the sensors array (which is on the surface of the femoral head) between the surface of the femoral head and the acetabulum of the prosthesis. The data is transmitted wirelessly by a low power transceiver. The display part demonstrates the contact distribution and the attitude of the prothesis in-vivo in 3-D images. The two parts of the system communicate with each other on a RF link at the band of 400MHz. The signal conditioning circuits have been designed and fabricated in 0.18μm CMOS process. The tested results show that the resolution of the signal conditioning circuits is 60.1μVpp (1.35g) with ±100mVpp input and the chip can operate under 1.2V to 3.6V voltage supply for single battery application with 116-160μA power current consumption. The system has been validated by experimental results.

This is the demonstration description of a wireless force measurement system for total knee arhtroplasty (TKA), which will be adopted in the operation to help the surgeons to place the implants quickly and accurately and consequently enhance the success ratio of treatment.

This paper focuses on high speed embedded SRAM design, especially on novel circuit technique to improve SRAM access time. A new two-stage sensing scheme which is able to reduce long interconnection metal line delay by transferring differential signals with half swing amplitude has been proposed. Post-layout simulation results show that the long distance signal transmission time has been decreased by 45%. Chip measurement shows the access time has been decreased by 23% at the expense of little area penalty (1.3%) and some read power penalty (about 16%) mainly caused by 2nd-stage sense amplifiers.

A wireless force measurement system is presented in this paper. The system, which is used during the operation of Total Knee Arthroplasty(TKA), is designed to assist surgeons to determine the proper position of the knee implants and consequently enhance the success ratio of the treatment. It consists of three parts: a device to measure and transmit force data, a receiver and a terminal to display the force data in real time. The transmitter communicates with the receiver by 2.4GHz Radio Frequency (RF) signal. The system consumes no more than 17mA current with 3V voltage supply typically. So it can work with a button battery cell. Experimental results show that the performance of the system meets the requirements.

A low-cost low-power baseband processor for passive UHF RFID Tag based on EPC C1G2 protocol is presented in this paper. In order to minimize the power consumption, a novel digital baseband architecture is proposed and a series of low-power design approaches are adopted, including asynchronous design, clock-gating, low operating frequency, reuse of registers, etc. The baseband processor supports eleven mandatory commands and one optional command (Access) and the C1G2 protocol is completely fulfilled. The whole Tag (including a 1K EEPROM, RF/Analog frontend and the low-power baseband processor) is fabricated in 0.18μm CMOS technology. Real measurements on the final chip indicate that the processor consumes less than 2.7μW at 1V supply voltage and occupies an area of 0.11 mm2.

A low-power CMOS capacitance-to-digital converter for capacitive sensors array is presented. It consists of a 16-channel MUX, a front-end with wide dynamic range for capacitance-voltage conversion and a novel voltage-pulses convertor. This novel circuit charges the measured capacitor indirectly and converts it into a proportional voltage, and then produces a 16-bits pulses-formed single-line output with multi-steps quantization method. The circuit can operate under 1.2V to 3.6V voltage supply for single battery application. The maximum input is 350pF with 0.75ms/ch update rate and 90μA power consumption when the operating clock is 100KHz. The chip has been design and fabricated in 0.18-μm 1P6M CMOS process with active area of 640×630μm2.

Integrated circuit (IC) design for a wireless BCI system is put forward in this paper. The system is composed of an electrode, a stimulator, antennas, and an integrated circuit including a preamplifier, an analog to digital converter (ADC), a current mode digital to analog converter (DAC), a transceiver and a micro control unit (MCU). The system is closed loop, which can detect and record electroencephalogram (EEG) signals, send the signals to computer wirelessly, and generate stimulating signals according to analysis results from the computer. A 16-bit ADC is designed and some non-idealities parameters (e.g. kT/C noise, 1/f Noise and so on) are given. Sub-threshold circuit technology is used to realize ultra low-power MCU. Both of the ADC and the MUC are verified by simulation results. Next work will include the design of the preamplifier, IDAC, and a single chip design integrating all the circuits.

Piezoelectric materials have been proposed as embedded power source, which are capable of converting mechanical energy into electrical energy. However, power generated from a piezoelectric material usually comes with poor characteristics such as high voltage, low current and high impedance. In order to drive the embedded sensor circuit, piezoelectric power needs to be characterized and regulated. In this paper, we present an analysis on the power generation characteristics of the stiff lead zirconate titanate (PZT) ceramics and its equivalent circuit. It is then verified by simulation and experimental results. Since a single PZT element may not meet the needs of real-world embedded applications, we present experiments and analysis using four identical PZTs. Finally, we outline an application where PZT elements are used for power generation in a Total Knee Replacement (TKR) implant.

A design of low power digital baseband for wireless endoscope capsule is presented. The key design issues involved in this IC are discussed, including implementation of communication protocol, real time image filter and real time JPEG-LS encoder. Power dissipation is lowered through the architectural exploration. The baseband has been implemented in 0.18 μm CMOS technology. Measurement results show that 50% power reduction is achieved when image compression is enabled @ 30 fps for VGA image at 1.2 V supply voltage compared with the situation when image compression is disabled, 11% power reduction is achieved compared with the previous research.

This paper proposes a new low complexity near-lossless image compression method and its VLSI design for low power and high frame rate in the wireless endoscopy capsule system. Assuring outstanding compression performance and high image quality, the proposed method with the features of low complexity, low storage overhead and real time data processing, makes it ideal for hardware implementation. The VLSI architecture consists of two pipelined parts: The preprocessor and the JPEG-LS engine. A fully pipelined VLSI structure with a dedicated clock management scheme is proposed for the JPEG-LS engine, which ensures a low power application, and real time data processing as well. The hardware implementation has been verified on FPGA and implemented in 0.18μm CMOS technology.