State of charge (SOC) and state of power (SOP) are two critical indices for lithium-ion batteries. Due to the complex operating environment in real applications, battery temperature can change significantly. This will lead to varied battery internal characteristics and pose a challenge for battery modelling and state estimation. This paper proposes an adaptive approach for battery online SOC and SOP co-estimation considering temperatures. First, a fractional-order multi-model system (FO-MMS) is constructed by integrating three sub-models at −5 Celsius, 20 Celsius, and 45 Celsius. To accommodate the battery current-voltage behaviors at different loads, SOCs, and temperatures, the contribution coefficient of each sub-model is adapted online through a temperature-embedded regularized moving horizon estimation algorithm. Second, a fractional-order multi-model proportional-integral observer (FO-MM-PIO) is designed for SOC estimation which achieves rapid convergence and suppresses external disturbances using the H-infinity criteria. Moreover, the nonlinear charge transfer dynamics of a battery under intense loads is simulated through the Butler-Volmer equation. An iterative approaching algorithm is then derived to estimate battery SOP in high fidelity. The experimental validations demonstrate that the proposed co-estimation method achieves the mean absolute error of less than 1.3% in SOC estimation and 2 W in SOP estimation, even at a sub-zero temperature (i.e., −5 Celsius).

Accurate state of charge (SOC) estimation of a battery pack is more meaningful than that of a cell in practical applications. The existing methods are difficult to provide an accurate SOC of a battery pack under a wide range of temperature due to cell inconsistency. In this paper, a SOC estimation method for a series-parallel lithium-ion battery pack based on the newly constructed OCV-SOC-temperature relationship was proposed. In the proposed method, firstly the cosine similarity is used to quantify cell inconsistency and the representative cells in the battery pack are determined by the largest cosine similarity value. Secondly, the OCV-SOC curves of the representative cells at different temperatures are used to construct the OCV-SOC-temperature relationship of the battery pack. Finally, a multi-branch fusion method is developed to estimate the SOC of the battery pack through the SOC of each branch by means of a Bayesian probability formula. The effectiveness of the newly constructed OCV-SOC-temperature relationship and the proposed SOC estimation method of the battery pack is verified under various dynamic conditions. The estimated SOC error of the series–parallel battery pack is less than 1.5%, which is approximately 60% lower than the traditional methods.

In this paper, a robust control scheme (RCS) for Steer-by-Wire (SbW) systems with partially known dynamics is proposed. It is shown that an SbW system can be represented by a nominal model and an unknown portion. A nominal feedback controller can then be used to stabilize the nominal model and a sliding mode compensator (SMC) is designed to remove the effects of both the unknown system dynamics and uncertain road conditions on the steering performance. For practical consideration, robust exact differentiator (RED) technique is utilized to estimate the derivatives of the position signals for controller design. It is further shown that the designed RCS is able to guarantee a robust steering performance against system and road uncertainties. The comparative experimental studies are given to verify the excellent performance of the proposed RCS for SbW systems.

Clock gating is one of the most effective techniques to reduce clock tree power. Although it has already been studied considerably, most of the previous works are restricted to either register transfer level (RTL) or clock tree synthesis stage. Clock gating design at RTL is coarse and it pays no attention to the physical information, therefore, it often results in large wirelength overhead. While if clock gating is considered only at clock tree synthesis, the optimization space is largely limited due to the fixing of registers. To fully use the logical and physical information between registers, we propose a new flow for low-power gated clock tree design in this work. It mainly includes three parts: gated clock tree aware register placement, gated clock tree construction, and incremental placement. Compared with the previous works on clock gating, our algorithm reduces the clock tree power with much fewer gating logics, therefore, the overhead to the placement is also reduced.

Clock gating is a popular technique for reducing power dissipation in clock network. Although there have been numerous research efforts on clock gating, the previous approaches still have a significant weakness. That is, they usually construct a gated clock tree after cell placement, i.e., cell placement is performed without considering clock gating and may generate a solution unfriendly to subsequent gated clock tree construction. As a result, the control gates inserted in the tree construction is very likely to cause cell overlap. Even though the overlap can be eventually removed in placement legalization, remarkable wirelength/power overhead is incurred. In this paper, we propose a gate planning technique which is integrated with a partition-based cell placer. During cell placement, the planning judiciously inserts clock gates based on power estimation. In addition, pseudo edges are inserted between clock gates and registers in order to reduce clock wirelength and enable long shut-off periods. At the end, when a relatively detailed placement is obtained, a post-processing is performed to degrade the inefficient clock gates to clock buffers. We compared our approach with recent previous works on ISCAS89 benchmark circuits. Our method reduces the clock tree wirelength and power by 22.06% and 40.80%, respectively, with a very limited increase on signal nets wirelength and power compared with the conventional (register-oblivious) placement. The results also indicate that our algorithm outperforms the clock-gating-oblivious placement [9] on power reduction and performance improvement.

Leakage power soars quickly as VLSI technology advance and supply voltage scaling, in the near future, it will exceed the dynamic power to become the main contributor of power dissipation. Previous methods on leakage power minimization always notice the negative effect of increasing the gate’s threshold voltage Vth, and the power reduction is obtained based on power and speed (or performance) tradeoff. However, increasing the gate’s Vth could be used to adjust the subtrees’ imbalance for a clock tree. In this paper, for a gated clock tree, we analyze the bottom up merging segment generation process and conclude the conditions for increasing the gate’s Vth. Our idea is trying to assign high Vthto the gates without total wirelength and performance overheads, and in some cases, it could even be used to get more balanced subtrees. Experimental results on a set of ISCAS89 benchmark circuits demonstrate that our algorithm could assign more than half of the gates with high Vth, the resultant leakage power reduction is more than 43% without any total wirelength and delay penalties.

Clock gating is one of the most effective techniques to reduce clock network power dissipation. Although it has already been studied considerably, most of the previous works are restricted to either logic level or clock routing stage. Due to the restriction, clock gating often meets the trouble of wirelength overhead and frequent control signal switching, both of which degrade its effectiveness. Furthermore, previous design flows which insert gate logics after placement introduce a lot of overlaps, especially when there are lots of gate logics inserted. In this work, we propose a new design flow for low power gated clock network construction, in order to minimize the clock wirelength and the activity of control signals, and to eliminate the overlaps incurred by the gate logics. Our method begins with a coarse placement followed by soft register clustering. Then, we perform clock tree topology construction and zero skew clock routing to further reduce the power and the clock skew. Last, the gated clock network is fed back to the placer for incremental placement. Experimental results on ISCAS89 benchmarks demonstrate that our method outperforms previous algorithm of activity aware register placement in clock wirelength and clock power reduction with signal nets wirelength and signal nets power increase within 5% and 3%, respectively

As a promising approach to mitigate the challenge of interconnect limit, X-architecture allows routings along diagonal directions in addition to rectilinear directions. It can reduce routing wire length and vias number compared with conventional Manhattan routing. Although Steiner minimum tree and signal routing algorithms have been developed for X-architecture, clock routing has not been addressed to the best of our knowledge. However, wire length reduction is even more compelling for clock net, as wire is a major power consumer and power supply noise generator. In addition, X-architecture is very effective for interconnect delay and clock skew optimization. In this paper, we investigate the layout embedding technique for clock routing in X-architecture and integrate it with the deferred-merge embedding (DME) algorithm. To alleviate the inaccuracy of the Elmore delay (ED) model, a more accurate fitted Elmore delay (FED) model is employed. Experimental results on benchmarks exhibit encouraging results.