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Patrick Conway

dblp:52/5299 · DBLP profile ↗
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4ranked-venue papers
1as first author
2since 2021 · last 2022
—ORCID · unresolved

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 2 · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 50% Integrated circuit design · 50%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › analog and mixed-signal circuits › device modeling
device model parameter extraction
0.011985
Extraction of MOSFET Parameters Using the Simplex Direct Search Optimization Method · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1985
Electronic design automation › circuit modeling
parameter extraction
0.011985
Extraction of MOSFET Parameters Using the Simplex Direct Search Optimization Method · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1985

Methods — techniques the papers use, named apart from their topics

simplex direct search optimization · 0.0
YearPublicationVenuePosition
2022 CAMP FHIR: Clinical Asset Mapping Program for FHIR
James Champion, Paul Kovach, Asiyah Ahmad, Anna Jojic, Buck Bohac, Adam M. Lee, Patrick Conway, Emily R. Pfaff
AMIA7
2022 Relational FHIR: Converting FHIR's Hierarchal Schema
Adam M. Lee, Paul Kovach, James Champion, Patrick Conway, Emily R. Pfaff
AMIA4
2007 A methodology for early validation of cache coherence protocols based on relational databases
abstract
Abstract A novel, table‐driven approach based on relational database technology is proposed for the design and early validation of cache coherence protocols. A protocol is specified as multiple communicating, multi‐input, multi‐output, finite‐state machines each represented by a relational database table. The tables are automatically generated by solving relational calculus constraints specifying the protocol transactions. Early protocol validation prior to an implementation is performed by testing these tables for several protocol properties expressed using relational queries and database integrity constraints. The debugged tables are automatically mapped to a high‐level hardware implementation while preserving their correctness. The proposed approach has been deployed at Fujitsu Systems Technology Division for the design of their next‐generation multiprocessor and has been highly successful in reducing the overall protocol development time and has discovered several errors early in the design cycle. Copyright © 2006 John Wiley & Sons, Ltd.
Mahadevan Subramaniam, Patrick Conway
Concurr. Comput. Pract. Exp.2
1985 Extraction of MOSFET Parameters Using the Simplex Direct Search Optimization Method
abstract
The method of extracting MOSFET model parameters using optimization offers significant advantages over classical methods of extracting model parameters sequentially. Previous work in this field has concentrated on speed of convergence rather than general applicability. Gradient following methods have been applied to this problem but difficulties arise because of parameter redundancy, singularities in the objective function, and the necessity of providing very good initial estimates of the model parameters. These factors can seriously hinder the application of the technique. This paper describes the application of the simplex direct search optimization method to this problem. This algorithm, in wide use for general optimization problems, needs no derivative calculation and has proved highly stable for MOS model parameter extraction. Its basis is described and an example of its use given.
Patrick Conway, Ciaran G. Cahill, William A. Lane, Sverre U. Lidholm
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1