By taking input from both a design description file and a file which contains the design rules of the target process, a silicon compiler software system can produce full artwork layouts for a variety of different processes. A specific example is used here to illustrate the complexities of incorporating the option of process independence in a system aimed at single metal interconnect CMOS.

This paper describes a programming environment in which gate array designs can be developed. It allows the engineer to design for performance, wirability and testability by manipulating a textual description of a design. The principle features of this are a high-level language for design description, completely automatic layout, and an integrated simulator. The total package can be referred to as a silicon compiler in the gate array design style.