Suspended sediment (SS) process can be used to explain reason for geological changes in the coastal area. To understand these processes, we analyzed the relationship between shoreline change and suspended sediment concentration (SSC). Landsat TM/ETM+ images were used for generating the map of suspended sediments concentration and shoreline change in this study. Landsat image has high spatial resolution and can provide 30 m-SSC images. As a result, shoreline changes in zone 2 and 3 show many variations for 20 years. SSC of Nakdong River is higher in zone 3 than in zone 1. It can be explained that SSC influence to shoreline and area change. However, to verify the result of the relationship between SSC and shoreline change, many data would be needed in the future.

Mt. Sakurajima in kagosima, japan is one of the most active volcanoes in the world. On 18 August 2013, the Sakurajima volcano recently went into the largest scaled eruption with a huge plume of volcanic ash. Therefore, the concern arises if this considerable amount of ashes might flow into the Korea peninsula as well as Japan. In this paper, we performed numeric experiment to analyze how volcanic product resulted from the Sakurajima volcano has impacted on Korea. In order to predict the spread pathway of ash, The Hybrid Single-Particle Lagrangian Integrated Trajectory (HYSPLIT) model and United Model (UM) data has been used and 17th September 2013 has been selected as observation date since it is expected that the volcanic ash would flow into the South Korea. In addition, we have detected ash dispersion by using optical Communication, Ocean and Meteorological Satellite- Geostationary Ocean Color Imager (COMS-GOCI) images. As the results, we come to a very satisfactory conclusion that the spread pathway of volcanoes based on HYSPLIT model are matched well with ash dispersion area detected from COMS-GOCI satellites image.

A new 3-D fuse architecture is proposed to improve the yield of 3-D memories. Because the 2-D memories are stacked to form a 3-D memory, the repair status of the prebond is kept as the good status. However, if faults occur in the postbond on the same cells which were repaired in the prebond, they must be identified and repaired because they cannot be repaired by the previous methods. There is no research on the repair the same faulty cells which occur in the prebond and postbond yet. Therefore, the new 3-D fuse architecture is proposed to repair the faulty cells which occur in the prebond and postbond. The redundancies which repair the faulty cells in the prebond are invalidated. The faulty cells are repaired by other redundancies in the postbond by the proposed 3-D fuse architecture. Thus, the proposed technique can improve the yield of 3-D memories. The experimental results show that the proposed technique can achieve higher yields of 3-D memories because only the proposed technique can repair the same faulty cells occurring in the prebond and postbond, and verify the good repair status of the 3-D memories.

A new built-in self-repair (BISR) scheme is proposed for multiple embedded memories to find optimum point of the performance of BISR for multiple embedded memories. All memories are concurrently tested by the small dedicated built-in self-test to figure out the faulty memories, the number of faults, and irreparability. After all memories are tested, only faulty memories are serially tested and repaired by the shared built-in redundancy analysis according to the sizes of memories in descending order. Thus, the fast test and repair are performed with low area overhead. To accomplish an optimal repair rate and a fast analysis speed, an exhaustive search for all combinations of spare rows and columns is proposed based on the optimized fault collection. Experimental results show that the proposed BISR has the optimal repair rate because of the exhaustive search. The performance of the proposed BISR is located in the optimum point between the test and repair time, and the area overhead. For example, the proposed BISR requires 49.6% of the area and 1.3 times of the test and repair time in comparison with parallel BISR scheme for four memories (one 128 K, two 256 K, and one 512 K memories). Furthermore, the more there are memories, the more superior performance in terms of the test and repair time, and the area overhead is shown.

A 3-dimensional Built-In Self-Repair (3D BISR) scheme is proposed for 3-dimensional (3D) memories. The proposed 3D BISR scheme consists of two phases: a parallel test-repair phase, and a serial test-repair phase. After all memory dice are simultaneously tested, only the faulty memory dice are serially tested and repaired using one Built-In Redundancy Analysis (BIRA) module. Thus, it is a faster test-repair with low area overhead. The proposed BIRA algorithm with a post-share redundancy scheme performs exhaustive searches for all combinations of spare rows and columns. Experimental results show that the proposed 3D BISR is up to two times faster than the 3D serial test-serial repair BISR when seven 2048 × 2048 bit memory dice are stacked. The proposed 3D BISR requires 44.55% of the area in comparison to a 3D parallel test-parallel repair BISR for four stacked memory dice (one 128 K RAM, two 256 K RAMs, and 512 K RAM). The yield of 3D memories is the highest due to the exhaustive search BIRA algorithm with the post-share redundancy scheme as shown in various experimental results.

3-D-stacked memory using through-silicon-vias (TSVs) has emerged as a good alternative for overcoming the limitation of 2-D memory technology. Among many issues with 3-D-stacked memory, yield is one of the major challenges for mass production. This paper proposes a new fuse architecture and redundancy scheme to improve the yield of 3-D-stacked memories. The new fuse architecture is developed based on the fact that the unused redundancies in prebond repair cause the inefficiency. Therefore, the new fuse architecture provides a way to share redundancies in prebond and postbond repairs. There are two kinds of operation modes. One is an enable mode for collecting the used redundancy information. The other is a mask mode for obtaining faulty redundancy information using a short test algorithm. Using the new fuse architecture, a new redundancy scheme called the post-share scheme is developed to achieve optimal yield. The post-share scheme allocates the fixed number of spare rows and columns for each repair just like other schemes. However, only allocated redundancies are used in prebond repair, while both the redundancies allocated for postbond repair and unused redundancies in prebond repair can be used for postbond repair. Experimental results show that the post-share redundancy scheme significantly increases the final yield of 3-D-stacked memories and the increase of area overhead is small.

Three-dimensional (3-D) memories using through-silicon-vias (TSVs) as vertical buses across memory layers has regarded as one of 3-D integrated circuits (ICs) technology. The memory dies to stack together in a 3-D memory are selected by a die selection method. In order to improve yield of 3-D memories, redundancy sharing between inter-die using TSVs is an effective strategy. With the redundancy sharing strategy, the bad memory dies can become good 3-D memories through matching the good memory dies. To support die selection and matching efficiently, a novel redundancy analysis (RA) algorithm, which considers various repair solutions, is proposed. Because the repair solutions can be various, the proposed die selection and matching is performed with two stages; general die selection and matching method in the first stage and re-matched remained memory dies, after the first stage, applying other repair solutions in the second stage. Thus, the proposed die selection and matching algorithm using the proposed RA algorithm can improve yield of 3-D memories. The experimental results show that the proposed die selection and matching method can achieve higher yield of 3-D memories than that of the previous state-of-the-art the die selection and matching methods.