A design support system is developed for engineering design based on the ontology which is declarative description conceptualized the world that agents (men and programs) focused on. The design process is understood as determining the design parameters and their relationships which consists the design model. The meta-model of design model is the ontology which represented as a network in the computer system using the XML. The design model is generated from the meta-model as class in Object oriented language . The system built with the above concept provides the following abilities, 1) declarative description that engineers intend to design, 2) effective entering data into Object oriented model, 3)semantic of design model which focused by numerical simulation and graphics programed with Java. Finally, the system's validity and effectiveness is ascertained by applying it to the basic design of an irrigation pipeline.

This paper discusses the architecture of the new Hitachi supercomputer series, which is capable of achieving 8 GFLOPS in each of up to four processors. This architecture provides high-performance processing for fine-grain parallelism, and it allows efficient parallel processing even in an undedicated environment. It also features the newly-developed time-limited spin-loop synchronization, which combines spin-loop synchronization with operating system primitives, and a communication buffer (CB) which caches shared variables for synchronization, thus allowing them to be accessed faster. Three new instructions take advantage of the CB in order to reduce the parallel overhead. The results of performance measurements confirm the effectiveness of the CB and the new instructions.

The authors discuss high-performance methods for solving first-order linear recurrences on a vector computer, investigate automatic transformations, and develop the compiling techniques for first-order linear recurrence problems. The results show that the improved vector code generated by the vectorizing compiler run at the rate of 150 MFLOPS (million floating operations per second), in the case of the moderate loop lengths (>1000), and at the rate of over 200 MFLOPS, in the case of long loop lengths (>10000), on the HITAC S-820 supercomputer. Overall performance improvements of 69% in the 14 Lawrence Livermore Loops and 25% in the 24 Lawrence Livermore Loops, as measured by the harmonic mean, are attained.>