Identification and removal of redundancy in digital circuits is important for improving their testability as well as reducing their area. This paper presents a method of identifying and removing redundancy in combinational circuits by analyzing circuit structure. Experimental results indicate that the method is quite efficient in execution time, but may not identify all undetectable faults. It is expected to be suitable for integration into a logic synthesis system. It can also be used as a preprocessor for a test pattern generation program or for a test pattern generation based redundancy removal program.>

Identification of undetectable faults is essential for preventing test invalidation due to the occurrence of such faults, and for improving the efficiency of test generation. Methods for identifying undetectable faults in combinational circuits by analyzing regions between fanout stems and reconvergent gates are presented. These methods have been successful in identifying many of the undetectable faults in several benchmark circuits, without test generation.>