Achieving race-free state assignments is an important objective in the synthesis of asynchronous sequential logic circuits (ASLCs). Traditionally, adjacency diagrams are used to help identify and resolve race conditions; however, this approach has a high degree of computational complexity. This paper presents an efficient state assignment algorithm that utilizes a pattern matching technique to predict races and to eliminate the need for enumerative searches. More specifically, the race-free state assignment problem is formulated as the embedding of a bipartite connected graph onto an n-cube and achieves a near minimum number of state variables. This algorithm has been evaluated using several representative examples. Results show that the developed algorithm provides better performance than existing algorithms. Due to the simplicity of the bipartite representation of an n-cube, the developed algorithm is suitable for ASLC synthesis that may involve a relatively large number of states.>

The paper proposes a divider structure that combines a novel self-timed ring structure and a carry-propagation-free division algorithm. The self-timed ring structure enables the divider to compute at a speed comparable to that of previously designed dividers with less silicon area. By exploiting the carry-propagation-free division algorithm, we can achieve even better performance. A 54-bit divider employing the proposed structure and algorithm was designed with 1.2 /spl mu/m CMOS technology. We obtained a speed of 215 ns per worst case division on 4.2 mm/sup 2/ of silicon area.>