This work investigates proposed maximum-powerpoint tracking (MPPT) approaches for a fully integrated hybrid voltage converter (H-VC) intended for alternative energy sources in low-power Internet of Things (IoT) systems, where passive components and power supply rail stability impose severe constraints. A monolithic Hybrid-Dual-Path (HDPC) voltage converter with an on-chip$L_{\text{DC}}=15.07 n H$inductor and strongly limited total capacitance ($C_{\text{IN}}=C_{\text{OUT}} \approx 2.5 n F$) is considered, with 1.5 V output voltage regulation provided by a continuously operating shunt-type regulator. The two MPPT concepts are analyzed: (i) iMPPT based on the fractional open-circuit-voltage (FOCV) principle, which is energy-efficient but requires periodic$V_{\text{IN,OC}}$sampling via short-time disconnection of alternative energy sources (AES), and (ii) oMPPT, which maximizes extracted load power by optimizing the combined product$\eta_{\text{MPPT}}.\eta_{\text{VC}}$and provides instantaneous power observability in a form of digital code. The feasibility and performance are evaluated in Cadence using a TSMC 65 nm CMOS technology and a realistic PV model (KXOB25-14X1F), across irradiance levels of 5-500 W/m2corresponding to PIN,MPPfrom$114 \mu W$to 14.8 mW. Simulation results show that both approaches regulate operation over a wide switching-frequency span of roughly 0.9-62 MHz via FrequencyShift Modulation Control (FSM-C). Overall, iMPPT is favored when minimal control overhead is paramount, whereas oMPPT offers superior scalability and algorithmic flexibility for broader AES applicability at the cost of up to 5.5 times higher power consumption.

This work presents the 1.2 V Low-Dropout Regulator (LDO) designed in a standard 65 nm CMOS technology using data obtained from experimental verification of 9 prototype chips. The measurement of standard parameters that were evaluated included Load Regulation (LDR) in the output current I out range from$\mathbf{1} \boldsymbol{\mu} \mathbf{A}$to$\mathbf{3 0 0} \boldsymbol{\mu} \mathbf{A}$, Line Regulation (LNR) at$\boldsymbol{I}_{\text {out }}$of$100 \mu ~\mathrm{A}$and$300 \mu ~\mathrm{A}$, Drop-Out voltage and PSRR parameter. In addition, the presented LDO dispose of a Slew-Rate Enhancement function, which can be activated externally. In all cases of this feature activation, the measurement proved its expected and correct function with reducing the settling time value and, depending on the direction of the output current change, also the voltage value for overshoot or undershoot.

This paper presents the design and measurement results of tunable Relaxation Oscillator ($\mathbf{R x O}$) proposed in standard 65 nm CMOS technology. The proposed RxO achieves the wide oscillation frequency range with fine tunability and low power consumption. The achieved results were obtained by measuring the prototype chip and show that the proposed oscillator can be tuned within the range of 72 kHz to 123 MHz, with a tuning step below 0.77 % for digital tuning and$0.53 \% / \text{mV}$for analog tuning with respect to the absolute value of the oscillation frequency. The low power consumption from$1 \text{nW} / \text{kHz}$to$23 \text{nW} / \text{kHz}$was observed. The figure of merit of 64 dB has been found to demonstrate an excellent dynamic range with fine tunability features.

This paper presents tunable voltage reference (TVR) designed in a standard general purpose 65nm CMOS technology. Designed circuit is based on two-transistor (2T) voltage reference (VR) with digitally controlled operational amplifier (OPAMP). Developed TVR provides stable output voltage from 0.38 V to 1.1 V with non-linear tuning step under 0.5% of the output voltage (from 1.9 mV to 2.9 mV). The supply voltage in the range from 0.91 V to 1.5 V is used. The circuit offers parameter PSRR = -53.59 dB (at 1 kHz) and line regulation (LNR) of 0.35% in the worst case. The required area is 0.0185 mm2. The proposed TVR was used to precise frequency tuning of oscillator. Provided results are obtained from both simulations and measurement of the manufactured ASIC prototype.

This work presents a dedicated method of analog integrated circuit (IC) autocalibration, which was used to calibrate a voltage reference with the output voltage value of 96 mV . The reference accuracy might be significantly influenced by fluctuations in the manufacturing process. The essence of this technique is to suppress this undesired influence of process variations in terms of the corner conditions of 130 nm CMOS technology. All analog parts of the proposed autocalibration system are presented at the transistor level. The output of the calibration subcircuit is a digital signal controlling the autocalibration.

In this paper, methods suitable for sensing the output load current (or current consumption) of analog circuits were studied and analyzed. The main focus was paid on approaches that can be implemented on a chip. The proposed approach for sensing the output current of a DC-DC converter is based on measuring the slope of a voltage sensed by an output bypass capacitor. Such an indirect sensing approach shows better efficiency than a common shunt resistor sensing method. The presented approach was used in a flyback type DC-DC converter. The simulated results prove better voltage conversion efficiency using the proposed indirect measurement approach.

This paper presents a novel on-chip digital method of calibration for a fully differential difference amplifier (FDDA), which is aimed at improved performance and reliability through enhanced robustness against variations of process parameters, voltage, temperature, and ageing drift. The proposed method was designed and verified within 130 nm CMOS technology design kit in Cadence environment. Calibration hardware is built-in with the calibrated FDDA, and the whole integrated system is able to operate with only 0.4 V power supply. The effectiveness of the proposed calibration method was examined mainly by evaluation of the FDDA input offset voltage using Monte Carlo, process corners and ageing analyses performed for the temperature range from -20° C to 85° C. The work established metrics for comparison of different calibration methods (i.e. digital calibration, chopper stabilization, analog calibration and autozero), which significantly differ in fundamentals of their operation. The proposed digital calibration outperforms its alternatives, while the precision of calibration, area and power consumption overhead are considered. The less advanced topology of digital calibration was previously implemented for variable-gain amplifier with considerable success (residual offset of the calibrated amplifier reaches fair levels of 13 μV to 167 μV). The concept proposed in this work utilizes advanced high precision calibration algorithm.

The paper addresses a development and evaluation of well-known EKV MOS transistor model with focus on the ultra low-voltage / ultra low-power analog IC design employing rather “exotic” bulk-driven technique. The presented contribution can be viewed as an extension of already established compact simulation model with modifications to the original parameter extraction flow. The article contains a brief description of EKV model fundamentals, a novel parameter extraction flow and most importantly, the comparison of developed EKV model with the foundry-provided BSIM model (v3.3) and the experimental measurement data obtained from prototype chip samples fabricated in 130 nm CMOS technology.

The paper addresses an evaluation of dynamic properties of silicon-proven ultra low-voltage/low-power rail-to-rail comparator fabricated in general purpose 130 nm CMOS technology. The experimental results confirm a correct operation at power supply voltage of VDD= 0.4 V and good agreement with post-layout simulation results can be observed. The proposed comparator topology has been proven to work in nW range and is also capable of operation with even lower power supply voltages and without a need of post-processing trimming. The article contains incremental results of performance analysis of discussed circuitry already published in [1].

This paper deals with cross-implementation of analytical and physical fundamentals of ultra low-voltage charge pumps. The analysis is based on precise, general formulas including characteristic parasitic effects valid for linear charge pumps. The parasitic effects are extended by non-linear parasitic capacitances represented as equivalent linear model of a switched transistor itself. The discussion about non-linear and linear behaviour of these parasitics is also included and demonstrated using cross-coupled, dynamic threshold implementation, where the EKV model of transistors has been utilized. The paper also introduced a new design rule for design of charge pumps based on transistors working in sub-threshold region to maximize the power throughput. This is achieved by tuning the operation conditions to the boundary case.

The paper addresses a novel topology of ultra low-voltage comparator with rail-to-rail input voltage range and selectable level of hysteresis designed in a standard twin-well 130 nm CMOS technology. The nominal power supply voltage of 0.4 V was used, and the working temperature range was set to the industrial standard from -20 °C to 85 °C. The proposed comparator design is intended to work in an energy harvesting system. Hence, low power consumption is the key requirement. The comparator employs bulk-driven transistors in the input stage and operates in so-called current mode. The designed comparator circuit draws less than 5 μA in typical conditions but its function and robustness have been verified across all possible process and temperature corners. The design was submitted to foundry for manufacturing and the measured data can be expected soon.

In this paper, a two-stage variable gain amplifier (VGA) based on bulk-driven approach is presented. The proposed VGA was designed using the bulk-driven technique, which brings a possibility to operate with ultra-low power supply voltage. In order to achieve rail-to-rail input voltage range, bulk driven input transistors are used. The proposed VGA was designed and implemented in 130 nm CMOS technology. Achieved results, which are obtained by simulation and experimental measurement of prototype chips indicate that the proposed VGA can be useful applied in low-voltage and low-power systems.

This paper addresses a design and performance evaluation of ultra low-voltage non-clocked voltage comparator. The circuit was designed in a standard twin-well 130 nm CMOS technology and is intended to work in temperature range of -20 – 85 °C with the power supply voltage of 0.6 V. The proposed comparator can handle the input voltage within the rail-to-rail range. Low-voltage design approaches, namely, g m /I D design methodology in combination with the bulk-driven operation approach have been employed. The measurements on fabricated prototype chips included evaluation of both static as well as dynamic parameters. An excellent correlation between simulations and the measured bench data was observed. The proposed comparator is currently being reviewed and re-designed for even lower power supply voltage of 0.4 V.

This paper presents design of the inverter-based driver for low-voltage applications, with topology for boosting the transistors overdrive voltage. The proposed driver topology was designed through detailed circuit analysis and optimization, and it is suitable for use in a switched capacitor charge pump. The driver was designed in 130 nm CMOS technology and verified by simulations including technology corners. Core of the proposed driver - the inverter uses power supply voltage of 200 mV. The whole boosted driver achieves a propagation delay of 9.2 ns and energy consumption of 92.12 μW for the value of load capacitor is 100 pF. Due to the low-power consumption, the proposed driver was satisfactory used in a self-powered charge pump systems.

In this paper, a variable gain amplifier designed in 130 nm CMOS technology is presented. The proposed amplifier is based on the bulk-driven approach, which brings a possibility to operate with low supply voltage (i.e. 0.6 V). Since the supply voltage of only 0.6 V is used for the amplifier to operate, there is no latchup risk that usually represents the main drawback of the bulk-driven approach. As an input stage, bulk driven transistors are used, which makes possible to operate in the rail-to-rail input voltage range. Achieved simulation results indicate that gain of the proposed VGA can be varied in a wide range, which together with the low supply voltage feature make the proposed amplifier useful for low-voltage and low-power applications.

An alternative method of fault simulation is presented in this paper. The proposed method is based on impedance calculations in the circuit under test. Calculation time and other properties of the method are addressed and evaluated. Possible application and results evaluation are demonstrated on an experimental circuit. This method could improve the test development time and quality.

In this paper, different topologies of gate-driven and bulk-driven current mirrors designed in 90 nm CMOS technology are presented. Since the conventional MOS transistors can work as a bulk-driven device, there is no need for any modification of the existing MOSFET structure or technology process. The bulk-driven current mirror is capable of operating at power supplies down to the threshold voltage of a standard MOS device. Bulk-driven current mirror topologies were compared to their gate-driven equivalents in terms of main properties and output characteristics. The achieved results prove that the bulk-driven design technique is very promising towards ultra low-voltage analog ICs.

Design of variable-gain amplifier (VGA), based on fully differential operational amplifier is presented. The proposed VGA topology was verified through simulations and analysis of main circuit parameters. The VGA is designed in 0.35 μm CMOS technology using Cadence environment and BSIM3 family of models. Designed circuit works with the power supply of 3.3 V. The simulation results show that gain bandwidth (GBW) of about 12 MHz (for capacitive load of 1 pF) and the total harmonic distortion of less than 1% for input amplitude 100 mV were achieved. Implemented feedback circuit is stable according to phase margin of 68.15°.

In this paper, a fully differential difference amplifier designed in 0.35 μm CMOS technology is presented. The proposed amplifier reaches high dynamic range and low input noise. Comparison of noise performance of the proposed fully differential difference amplifier to an ordinary differential amplifier has been performed. Simulation results prove that the developed amplifier circuit can be advantageously used in applications that require a fully differential signal. In our work, the proposed amplifier has been experimentally employed in the analog front end of the readout interface for a MEMS (Micro-Electro-Mechanical-Systems) capacitive microphone.

A novel resistance calculation method based on eigen calculus of the circuit's nodal admittance matrix is described and evaluated in this paper. More specifically, the calculation time efficiency of the method is examined and comparison to the traditional LU factorization based method is made. This evaluation is based on real and complex matrices that are both symmetrical and non-symmetrical as well. Circuits sizes taken into account range from 25 to 3600 nodes. The obtained results demonstrate the time efficiency of this method, especially, for non-symmetrical matrices. The proposed method could be used to speed-up the fault simulations and improve test development of analog circuits.

The paper deals with a new approach to selection of the optimum value of the oscillation frequency towards increasing the efficiency of the oscillation-based test methods in covering hard-detectable short faults in nanoscale technologies. For this purpose, the Describing-Function analysis was used to calculate of the oscillation frequency of a simple oscillator (an analog circuit under test) modeled in MATLAB. Accuracy of the model was evaluated through comparison of computed parameters to parameters achieved for the same circuit in Cadence.

Research presented in this paper is aimed at the comparison of the Oscillation-based Built-In Self Test (OBIST) efficiency in covering catastrophic and parametric faults in active analog integrated filters designed in two different technologies. Sallen-Key topologies of low-pass and high-pass filters were used as Circuit Under Test (CUT), designed in 0.35μm and 90nm CMOS technologies. The presented oscillation test strategy uses the on-chip Schmitt oscillator as the reference frequency source to compensate the influence of process parameter variations. Achieved results show that the proposed BIST approach is fully implementable in nanoscale technologies. Finally, dependence of the fault coverage on the oscillation frequency value was investigated.

This paper deals with comparison of two discrete methods for digital trimming of the input offset voltage in operation amplifiers designed in 90nm CMOS technology. Two different topologies based on the binary weighed ladder, one using successive approximation register (SAR) and the other employing a simple counter, were compared. Furthermore, a correction circuit was proposed and used to form the mean offset voltage and increase the probability that its value after trimming process will be near zero. Finally, achieved results and improvements are discussed.

This paper deals with the comparison of the fault coverage of catastrophic faults in active analog integrated filter obtained by the measurement of filter parameters and by the Oscillation-based Built-In Self Test (OBIST) approach. In our experiment, firstly, the cut-off frequency, ripple in the pass band, DC gain in pass band and group delay of the filters have been monitored in the operating mode. Then, during the test mode (OBIST), the filter is transformed to an oscillator, and the oscillation frequency is compared to the frequency from a dedicated on-chip reference oscillator to compensate undesired influence of technology variations. The obtained results on the efficiency of both approaches are compared.

Dynamic supply current test method (IDDTtest) in static random access memory (SRAM) cell arrays is addressed in order to unveil weak open defects. Simulations were carried out on a 64-bit SRAM circuit, where several parameters of the IDDTwaveform were monitored. The SRAM circuit was designed in a 90 nm CMOS technology. Efficiency of IDDTtest in unveiling open defects was evaluated and the achieved results were compared for four SRAM arrays with cells of different cell ratio (CR). Moreover, a solution for transformation of the dynamic current to voltage is presented. After the transformation of the current waveform to a voltage waveform, the parameters of the voltage waveform similar to those of the current waveform are easily monitored and evaluated.

A new strategy for on-chip test of an operational amplifier as a part of complex analog and mixed-signal systems is described. During test mode, the operational amplifier is disconnected from the rest of the circuit and transformed to an oscillator. To evaluate the circuit, its oscillation frequency is then compared to a frequency given by a Schmitt trigger oscillator, used as the on-chip reference to compensate technology variations. This method might bring a possibility to implement the Oscillation-based Built-In Self-Test (OBIST) for operational amplifiers as a part of complex systems.

The paper deals with dynamic supply current (iddt) test method, where several parameters of the iddt waveform have been monitored. Simulations were performed on two 64-bit SRAM circuits, in which resistive open defects were investigated. The technologies used were 0.35 µm and 90 nm CMOS. The efficiency of iddt test in covering open defects for both technologies was evaluated.