The rapid growth of data-intensive applications has motivated the exploration of Processing-in-Memory (PIM) as a means to overcome memory bandwidth limitations in modern systems. By integrating processing units directly into DRAM chips, PIM enables computation close to the row buffers, reducing costly data transfers to the CPU and alleviating the memory wall. Within this context, sorting is one of the most fundamental building blocks in databases, analytics, and large-scale computing. Despite its bandwidth-intensive nature, it remains largely unexplored on commercial PIM hardware. In this work, we present UPSort, the first sorting algorithm designed and implemented on commercial PIM DIMMs. UPSort adopts a PIM-CPU cooperative model, leveraging PIM’s data-level parallelism for pre-sorting large blocks while delegating the final merging to the CPU. This design overcomes key architectural constraints of PIM DIMMs, including limited communication and fine-grained data transfers. Our evaluation on UPMEM PIM demonstrates that UPSort achieves up to $7.2 \times$ speedup over qsort, and on average $3.9 \times$ improvement compared to state-of-the-art algorithms such as BlockQuicksort and Quadsort. These results highlight the potential of PIM-CPU cooperative execution as a practical and efficient strategy for accelerating fundamental algorithms in future memory-centric systems.

Contemporary Vector Processors (VPs) are de-signed either for short vector lengths, e.g., Fujitsu A64FX with 512-bit ARM SVE vector support, or long vectors, e.g., NEC Aurora Tsubasa with 16Kbits Maximum Vector Length (MVL1). Unfortunately, both approaches have drawbacks. On the one hand, short vector length VP designs struggle to provide high efficiency for applications featuring long vectors with high Data Level Parallelism (DLP). On the other hand, long vector VP designs waste resources and underutilize the Vector Register File (VRF) when executing low DLP applications with short vector lengths. Therefore, those long vector VP implementations are limited to a specialized subset of applications, where relatively high DLP must be present to achieve excellent performance with high efficiency. Modern scientific applications are getting more diverse, and the vector lengths in those applications vary widely. To overcome these limitations, we propose an Adaptable Vector Architecture (AVA) that leads to having the best of both worlds. AVA is designed for short vectors (MVL=16 elements) and is thus area and energy-efficient. However, AVA has the functionality to reconfigure the MVL, thereby allowing to exploit the benefits of having a longer vector of up to 128 elements microarchitecture when abundant DLP is present. We model AVA on the gem5 simulator and evaluate AVA performance with six applications taken from the RiVEC Benchmark Suite. To obtain area and power consumption metrics, we model AVA on McPAT for 22nm technology. Our results show that by reconfiguring our small VRF (8KB) plus our novel issue queue scheme, AVA yields a 2X speedup over the default configuration for short vectors. Additionally, AVA shows competitive performance when compared to a long vector VP, while saving 50% of area.

A method of FPGA implementation of the class of parametric digital conjunctions defined by (p)-monotone sum of basic t-norms is proposed. The paper presents the logical diagrams of parametric digital conjunctions developed by means of VHDL language in Quartus II with ModelSim software of Altera. Parametric digital conjunctions can be used in reconfigurable digital fuzzy systems where the parameter p and a sequence of basic t-norms used in definition of parametric conjunction can be changed.

Fuzzy theory applications have been explored and analyzed on fields as pattern recognition, control, data classification, signal processing, expert systems, among others. To accomplish this, more complex calculations and faster processing speed are required, turning fuzzy hardware implementation to be the perfect choice. Fuzzy operations as t-norms and t-conorms are used in fuzzy systems as conjunction and disjunction operations respectively. Commonly used t-norms for hardware implementation are minimum and algebraic product, first one is cheaper to implement; second consumes more resources. On this work FPGA technology is used to implement basic fuzzy t-norms as minimum, Lukasiewicz and drastic product into an 8 bit single circuit that allows operation selection. Timing, resources and comparative results are presented.

Instruction queues consume a significant amount of power in a high-performance processor. The wakeup logic delay is also a critical timing parameter. This paper compares a commonly used CAM-based instruction queue organization with a new pointer-based design for delay and energy efficiency. A design and pre-layout of all critical structures in 70nm technology is performed for both organizations. The pointer-based design is shown to use 10 to 15 times less power than the CAM-based design, depending on queue size, for a 4-wide issue, 5GHz processor. The results also demonstrate the importance of evaluating all steps of instruction queue access: allocation, issue and wakeup rather than wakeup alone, especially for power consumption.

Abstract In this paper, we study the workspace awareness in a groupware application allowing the development of an information task through collaborative debates. The application, called CDebate, is based on the APRI (Action–Perception–Reflection–Intention) model, which establishes a cognitive and motor states organization that occurs when humans are interacting with one another in a constructivist and collaborative learning situation. In CDebate, the interactions among students occur through a graphical language that reflects the mental operations appropriate for a debate. As an evaluation method, a conceptual framework, which provides a set of elements that give information about the up-to-the-moment knowledge about participants' location and actions, is used. The results of this study allow us to confirm that group awareness information, supported through a graphical language and a window showing the participants' presence (informal awareness), were sufficient for success in the collaborative learning situation. This experience could be useful for interface designers of groupware applications, in particular for collaborative debate interfaces.

7'1~is paper presents a study oj the impact of reducing the vector register length in an out-o,f-order vector architecture.In hditional in-ol,der vector