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Robert J. Holwill

dblp:53/2467 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1992
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 87% Integrated circuit design · 13%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
physical design		 0.011992
A yield improvement technique for IC layout using local design rules · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992
Electronic design automation › design for manufacturability › design for yield
yield enhancement		 0.011992
A yield improvement technique for IC layout using local design rules · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992
Integrated circuit design › VLSI design
IC layout		 0.011992
A yield improvement technique for IC layout using local design rules · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992

Methods — techniques the papers use, named apart from their topics

track width adjustment · 0.0track displacement · 0.0contact size adjustment · 0.0
YearPublicationVenuePosition
1992 A yield improvement technique for IC layout using local design rules
abstract
The concept of local design rules is introduced. These are integrated circuit (IC) layout rules that define the optimum feature size and spacing in relation to the surrounding geometry and are used to increase the yield of ICs. The impact of these rules on the performance and reliability of ICs is discussed. Algorithms that enable the automatic application of track displacement, track width, and contact size local design rules to IC layout are presented. Simulation results are provided for some layout examples.>
Gerard A. Allan, Anthony J. Walton, Robert J. Holwill
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3