The subthreshold circuit is a practical design style for the ultralow-power applications, but its timing estimation is a challenge due to the increasing local variation effects. The delay variation of adjacent gates is not independent because of input slew variation caused by the precedent gate, so their correlation effects are difficult to model and estimate. This article proposes a semi-analytical statistical delay model considering local variation for the subthreshold region, that is, the combination of analytical and simulation-based method. First, it decorrelates the slew influence between adjacent stages by dividing delay and output slew model into fast/slow input cases and dividing delay variation model into process variation and input slew variation. Then, it can be applied into multi-PVT conditions with a one-time SPICE nominal simulation by analyzing the independence of variability and relative variability of step input gate delay variance with output load capacitance and process, voltage, and temperature (PVT). Finally, experiments are carried out for different benchmarks, processes, voltages, and temperatures (BPVTs). The average errors of variance on different BPVTs are 4.8%, 3.1%, 4.0%, and 4.7%. Compared with other analytical works, the accuracies' improvements of three metrics (variance, variability, and max delay) are 8.3×, 9.6×, and 2.7× by the mean error at all test benchmarks. Compared with industrial method LVF, it has a comparable error in max path delay and runtime, and less three orders of magnitudes than LVF in characterization time and stored data (from TB to GB) at all test benchmarks.

Subthreshold circuit has the significant advantage in low-power applications but suffers from serious variation increase. Traditional EDA tools could not achieve balance between accuracy and simulation effort for statistical timing analysis in subthreshold region. Many researches have been devoted to statistical timing model to reveal the relation between delay variation and process variation with physical insight. However, the statistical correlation of gate delay in circuit path is hard to capture and not considered appropriately in most prior works. In this paper, a statistical timing model for subthreshold circuit is proposed with the consideration of local process variation and correlated variation from adjacent gates, which is established by deriving variance models for gate delay and output waveform analytically for fast and slow input waveform separately, so that the path delay variation can be translated from the accumulation of the correlated gate delays with input slew to a linear combination of independent step input delays. The proposed model was verified under the process of TSMC28nm technology at the subthreshold supply voltage with the estimation error of less than 6% for circuit path delay variation in benchmark ISCAS99 compared with Monto Carlo simulation results, which outperforms prior works with 5~10X accuracy increase and acceptable simulation cost.

The increasing performance variation and non-Gaussian distribution pose remarkable challenges to timing analysis for circuits operating in low voltage region. Accurate modeling of the statistical characteristics is urgently required with process variation consideration. In this paper, the statistical models for drain current and gate delay in low voltage region are established in analytical form based on the log-skew-normal (LSN) distribution via moment matching technique. Experimental results show that the probability distribution function (PDF) curves obtained from the proposed models for drain current and gate delay are highly fitted with Monte Carlo (MC) simulation results in sub/near-threshold regions. Moreover, owing to the proposed LSN-based statistical model, less than 8% error is introduced in the predicted sensitivity of gate delay and the maximum/minimum delay indicated by ±3σ percentile points can be calculated more precisely than the LN-based method with up to 3× accuracy improvement for low supply voltage.

Near-threshold voltage (NTV) design suffers severe challenge due to the dramatic increase in performance uncertainty introduced by process variation. This paper proposes an analytical approach based on Log-Normal (LN) distribution to characterize the statistical delay for NTV design considering the dominant threshold voltage variation from gate-level to circuit-level. At gate-level, the multivariable threshold voltage variation issue is solved by the equivalent threshold voltage method and equivalent drain current method for generic gates with stack topology and parallel topology, respectively. At circuit-level, a statistical timing model is proposed as the linear combination of the independent statistical delays of all gates in the path with step input by considering the varied correlation between adjacent gates. To the best of our knowledge, we firstly propose a statistical timing model analytically for practical circuit path with physical insights of supply voltage, transistor size, and load capacitance. The characterization effort for each path is only one-time SPICE simulation, which is negligible compared with Monte Carlo (MC) simulation in statistical static timing analysis (SSTA) methods. Experimental results under a commercial 28-nm CMOS process show the proposed models have high accuracy at low supply voltage compared with MC simulations, where the modeling errors for the mean and variance of gate delay can be limited within 1.54% and 11.2%, respectively. Moreover, as for the practical paths in ITC'99 benchmark, the maximum modeling errors of mean, variance, minimum delay, and maximum delay is less than 3.04%, 11.40%, 4.50%, and 2.87%, respectively.