As we move to higher carrier frequencies, directional wireless networks using planar arrays with many antenna elements will become common. Directional radios have been implemented using a variety of antenna array geometries. While it is clear that the optimal choice of array geometry is effected by the physical extent of the network space, there has been limited study of the interaction of array geometry and system performance under the realistic assumption of a finite operating space. In this study, we examine antenna array geometries in directional wireless networks and their effect on interference using probabilistic analysis. We treat the nodes as having a uniform distribution in a given physical space and calculate the expected interference. We observe that linear antenna arrays, independent of position, perform significantly better than other rectangular antenna array geometries given a fixed number of antennas.

We consider networks consisting of nodes equipped with large antenna count mmWave arrays enabling narrow beam patterns. For the first time, we investigate and quantify the adverse impact of interference on network capacity for these very narrow beams. Network capacity is studied in terms of both node density as well as antenna array size. Finally, we show a distributed adaptive receiver algorithm that can reduce the adverse interference impact up to 60%.

mmWave (millimeter-Wave) is a very promising technology for the future wireless communication. To mitigate its high attenuation characteristics, mmWave communication frequently employs directional beamforming for both transmission and reception. Localization commonly takes advantage of directionality in RF frequencies in urban and indoor environments. In this paper, we use lessons learned from classical RF-based localization for discussing a set of feasible localization approaches in the context of mmWave bands. We further map the requirements of each discussed localization approach to design requirements for future mmWave devices and assess the expected accuracy of such approaches for a set of realistic scenarios. Our results show that mmWave-based localization is promising in both its availability and accuracy, even in the presence of a limited number of localization anchor nodes.

This paper presents the design of BORPH's file system layer for FPGA-based reconfigurable computers. BORPH provides user FPGA designs that execute as hardware processes access to the general file system using familiar UNIX file I/O semantics. Such capability provides FPGA designers an intuitive interface not only for regular file I/O, but also for representing streaming hardware/software and hardware/hardware communication using UNIX pipes. Design trade-offs among system manageability, user usability and application performance are explored. A case of mixed hardware/software video processing is presented as a proof-of-concept.

Large-scale, direct-mapped FPGA computing systems are traditionally very difficult to debug due to the high level of parallelism and limited access to internal signal values. This poster describes our solution to this problem, in which the concepts of variables and process control are brought into the FPGA hardware domain. Declarations made in the design environment are translated into logic inserted automatically into the hardware implementation. Variables provide full read/write access to hardware signals during runtime, complete with dynamic assertion checking capable of automatically halting the system clock. System data is consistently cached via attached DRAM, providing a very deep history of variable sample values and the ability to "rewind" system state. Process execution can also be controlled by the user on a cycle-by-cycle basis, either manually or through the declaration of breakpoints. Assertion failures and breakpoints are accurate within the same cycle of detection, and are implemented using on-chip gated clock buffers. All debugging controls are provided by a remote graphical user interface, which also supports back-annotation in the input design for improved data visibility and comprehension. The complete hardware and software infrastructure of the debugger has already been fully implemented, with user trials and overhead measurements ongoing at the time of writing

Large-scale, direct-mapped FPGA computing systems are traditionally very difficult to debug due to the high level of parallelism and limited access to internal signal values. In our approach to mitigate this problem, the concepts of variables and process control are brought into the FPGA hardware domain. Declarations made in the design environment are translated into logic inserted automatically into the hardware implementation. Variables provide full read/write access to hardware signals during runtime, complete with same-cycle, dynamically definable assertion checking. System data is cached via attached DRAM, providing deep variable history and the ability to ldquorewindrdquo system state. Process execution can also be controlled by the user manually or through the declaration of breakpoints. All debugging controls are available via a remote graphical user interface, which also supports back-annotation in the input design for improved data visibility and comprehension. Empirical examples have shown the logic overhead for the above functionality to be approximately 66 slices per 16-bit variable with full assertion checking on a Virtex-II Pro device, plus the fixed requirements of the debug controller and memory interface.

This paper presents the design and implementation of BORPH’s kernel file system layer that provides FPGA processes direct access to the general file system. Using a semantics resembling that of conventional UNIX file I/Os, an FPGA accesses the file system through a special hardware system call interface. By extending the semantics of a UNIX pipe, a single file system access mechanism is used for both regular file I/O, as well as for hardware/software and hardware/hardware data streaming. An FPGA design may switch between different communication modes dynamically during run time by means of file redirection. Design trade-offs among system manageability, user usability and application performance are explored. An example of constructing a video processing system during run time using commodity software and FPGA applications connected by pipes is used to demonstrate the feasibility and potential of such FPGA-centric file system access capability.

This paper explores the design and implementation of BORPH, an operating system designed for FPGA-based reconfigurable computers. Hardware designs execute as normal UNIX processes under BORPH, having access to standard OS services, such as file system support. Hardware and software components of user designs may, therefore, run as communicating processes within BORPH's runtime environment. The familiar language independent UNIX kernel interface facilitates easy design reuse and rapid application development. To develop hardware designs, a Simulink-based design flow that integrates with BORPH is employed. Performances of BORPH on two on-chip systems implemented on a BEE2 platform are compared.

Ultra-wideband (UWB) impulse radio is a promising technique for low-power bio-medical communication systems. While a range of analog and digital UWB architectures exist, the mostly-digital approach without analog down-conversion enables better technology scaling and signal processing flexibility. Furthermore, recently proposed sub-sampling schemes and advances in high-speed ADC circuit design are helping to make this approach more feasible at low power. However, architectures that directly sample the received signal are more vulnerable to sampling jitter. Currently, there does not exist a model describing the impact of sampling jitter making it difficult to determine appropriate tolerances or to establish the feasibility of digital architectures. To address this problem, we have developed a model of sampling jitter and derived a generic bit error rate expressions for a digital UWB modem with sampling jitter, additive noise, and imperfect channel estimation in a generic multipath environment. We then use this model to investigate the performance of sub-sampled digital UWB in a body area network. This paper explains this analytical model and compares it with simulations results for communication around the body.

The discrepancy between perceived spectrum shortage from the FCC allocation map and the actual abundance of available spectrum is a motivation for Cognitive Radios, which locate and transmit in the unused or lightly used bands. If a digital approach is taken to provide the necessary radio flexibility to exploit this sparsity, there is a challenging dynamic range requirement in the analog to digital conversion, since there are large interfering signals which are effectively in-band and can not be removed by fixed RF pre-filtering. Using a mixed analog digital system architecture which uses multiple low accuracy ADCs with digital adaptive filters, it is possible to increase the effective dynamic range of the input by subtracting off the unwanted signals in the time domain.

This panel discusses the following topics. With the ongoing trend towards more and more digitization in applications ranging from multimedia to telecommunications, there is a big debate about whether there will remain a need for analog circuits in scaled technologies. Analog circuits do not seem to take advantage of nanometer CMOS; rather they suffer from it. So if the question is asked "Will analog scale?", you get conflicting opinions. One camp argues for an almost-all-digital future: analog/RF content should be limited, because it's difficult, expensive, risky, and can be done with DSP. The opposing camp counters that some critical circuits simply do not want (or need) to scale, and analog is only "risky" when you let digital designers do it. So, what is the future role of analog circuits in scaled CMOS, and can analog EDA tools help in this .

Advances in FPGA-based reconfigurable computers have made them a viable computing platform for a vast variety of computation demanding areas such as bioinformatics, speech recognition, and high-end digital signal processing. The lack of common, intuitive operating system support, however, hinders their wide deployment. This paper presents BORPH, an operating system framework for FPGA-based reconfigurable computers with a goal to ease and accelerate development of high-level applications to run on these computers. It provides kernel support for FPGA resources by extending a standard Linux operating system. Users therefore compile and execute hardware processes on FPGA resources the same way they run software processes on conventional processor-based systems. The operating system offers run-time general file system support to hardware processes as if they were software. Furthermore, a virtual file system is built to allow access to memories and registers defined in the FPGA, which provides communication links with running hardware processes. Increased productivities have been observed for high-level application developers, who have few previous experiences in hardware design, to implement complex mixed software/hardware designs on a FPGA-based reconfigurable computer running BORPH

This paper describes the digital complex signal processing techniques for a pulse-based UWB radio. The proposed baseband is essential to fully exploit the wideband signal characteristics as well as compensating the analog front-end impairments. The property and optimal usage of these signal processing blocks are analyzed for both data detection and precision ranging applications. The same signal processing approaches are applicable for baseband and passband UWB communications as both are of interest under FCC regulations.

A methodology for VLSI realization of signal processing algorithms for wireless communications is presented that optimizes architecture for reduced power and area. When power is limited, optimal architecture represents a point on the best power-area tradeoff curve that is obtained by balancing the algorithm throughput with the power-performance tradeoff of the underlying building blocks. Architectural optimization is done in the graphical Matlab/Simulink environment, which is also used for algorithm verification. Hardware description language produced by Simulink enables algorithm emulation on the FPGA and also serves as design entry for the chip realization. This is illustrated on complex multi-dimensional algorithms such as wideband MIMO channel decoupling through singular value decomposition (SVD) using 16 sub-carriers.

Cognitive Radios have been advanced as a technology for the opportunistic use of under-utilized spectrum since they are able to sense the spectrum and use frequency bands if no Primary user is detected. However, the required sensitivity is very demanding since any individual radio might face a deep fade. We propose light-weight cooperation in sensing based on hard decisions to mitigate the sensitivity requirements on individual radios. We show that the "link budget" that system designers have to reserve for fading is a significant function of the required probability of detection. Even a few cooperating users (~10-20) facing independent fades are enough to achieve practical threshold levels by drastically reducing individual detection requirements. Hard decisions perform almost as well as soft decisions in achieving these gains. Cooperative gains in a environment where shadowing is correlated, is limited by the cooperation footprint (area in which users cooperate). In essence, a few independent users are more robust than many correlated users. Unfortunately, cooperative gain is very sensitive to adversarial/failing Cognitive Radios. Radios that fail in a known way (always report the presence/absence of a Primary user) can be compensated for by censoring them. On the other hand, radios that fail in unmodeled ways or may be malicious, introduce a bound on achievable sensitivity reductions. As a rule of thumb, if we believe that 1/N users can fail in an unknown way, then the cooperation gains are limited to what is possible with N trusted users.

In ultra-wideband (UWB) systems, antennas act as filters that introduce a frequency dependent response from the transmitter to receiver. To capture the waveform dispersion so that one can equalize/compensate at the transmitter/receiver, a new circuit modeling methodology that handles omnidirectional small antennas is proposed. By transforming the antennas into the degenerated Foster canonical forms and utilizing the waveform-omnidirectional property, it is shown that the transmitted far field waveform is a scaled version of the voltage across the radiation resistor in the model. Extended Thevenin/Norton equivalent circuits with dependent sources tracking the frequency dependence of the antenna effective length are also built for UWB receiving antennas. Simulation and experimental results show that this methodology is effective over a wide bandwidth and suitable for modeling most UWB antennas.

The impact of scattering condition and array configuration on performances are inseparable in early analyses of multiple-antenna systems. An array-independent scattering model is introduced where three basic scattering mechanisms are modeled. Performance results become more intrinsic property of the scattering channel itself. For linear arrays of length L in an environment of total angle spread |Omega|, the ergodic capacity is shown to increase linearly with L|Omega| for large arrays. When antenna arrays reduce to practical sizes, the capacity scaling depends on the signal-to-noise ratio (SNR) as well. This implies that the number of antennas used should also depend on the SNR. In terms of outage capacity, the tradeoff between spatial multiplexing gain and diversity gain is shown to be very sensitive to the underlying scattering mechanisms. Finally, as |Omega| varies with the propagation range, the tradeoff among multiplexing gain, diversity gain, and propagation range is studied

Cognitive radio systems offer the opportunity to improve spectrum utilization by detecting unoccupied spectrum bands and adapting the transmission to those bands while avoiding the interference to primary users. This novel approach to spectrum access introduces unique functions at the physical layer: reliable detection of primary users and adaptive transmission over a wide bandwidth. In this paper, we address design issues involved in an implementation of these functions that could limit their performance or even make them infeasible. The critical design problem at the receiver is to achieve stringent requirements on radio sensitivity and perform signal processing to detect weak signals received by a wideband RF front-end with limited dynamic range. At the transmitter, wideband modulation schemes require adaptation to different frequency bands and power levels without creating interference to active primary users. We introduce algorithms and techniques whose implementation could meet these challenging requirements.

Multiple-antenna systems that are limited by the area and geometry of antenna arrays, are considered. Given these physical constraints, the limit on the available number of spatial degrees of freedom is derived. The commonly used statistical multiple-input multiple-output (MIMO) model is inadequate. Antenna theory is applied to take into account the area and geometry constraints, and to define the spatial signal space so as to interpret experimental channel measurements in an array-independent but manageable description of the physical environment. Based on these modeling strategies, for a spherical array of effective aperture A in a physical environment of angular spread |/spl Omega/| in solid angle, the number of spatial degrees of freedom is shown to be A|/spl Omega/| for uni-polarized antennas and 2A|/spl Omega/| for tri-polarized antennas. Together with the 2WT degrees of freedom for a system of bandwidth W transmitting in an interval T, the total degrees of freedom of a multiple-antenna channel is therefore 4WTA|/spl Omega/|.

A tool that automates the floating-point to fixed-point conversion (FFC) process for digital signal processing systems is described. The tool automatically optimizes fixed-point data types of arithmetic operators, including overflow modes, integer word lengths, fractional word lengths, and the number systems. The approach is based on statistical modeling, hardware resource estimation and global optimization based on an initial structural system description. The basic technique exploits the fact that the fixed point realization is a weak perturbation of the floating point realization which allows the development of a system model which can be used in the optimization process.

We present a method for designing operational amplifiers using reversed geometric programming, which is an extension of geometric programming that allows both convex and non-convex constraints. Adding a limited set of non-convex constraints can improve the accuracy of convex equation-based optimization, without compromising global optimality. These constraints allow increased accuracy for critical modeling equations, such as the relationship between gm and IDS. To demonstrate the design methodology, a folded-cascode amplifier is designed in a [0.18]μm technology for varying speed requirements and is compared with simulations and designs obtained from geometric programming.

This paper describes a signal processing technique which allows a reduction in the complexity of a transceiver for a 3.1-10.6 GHz ultra-wideband radio. The proposed system transmits passband pulses using a pulser and antenna, and the receiver front-end downconverts the signal frequency by subsampling, thus requiring substantially less hardware than a traditional narrowband approach. By exploring the properties of analytic signals, the system allows hardware reduction and a time resolution finer than the sampling period, which is useful for locationing or ranging applications.

Most existing analyses of quantization effects are given under the condition that all decision-making blocks, if they exist in a system, produce identical decisions in both fixed-point and infinite-precision (IP) implementations. However, in doing floating-point to fixed-point conversion (FFC), a fixed-point design with occasional decision errors may still be an acceptable approximation of the IP system. We study the effect of this decision error, and relate its probability to the fixed-point data types. Our previous FFC methodology is then extended to include systems with possible decision errors due to quantization. The extended approach is applied to both CORDIC and a BPSK transceiver.

This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (Field Programmable Gate Array) based emulation engine with a capacity of 10 million ASIC (Application Specific Integrated Circuits) equivalent gates. Attainable system operation frequency can exceed 60 MHz, and the system throughput has been empirically verified to achieve 600 billion 16-bit additions per second. The emulator is custom designed to maximize the performance and resource utilization for a range of telecommunication and digital signal processing applications. With its high-speed interconnect architecture and large external I/O bandwidth, the emulator excels in prototyping real-time systems that have strict timing, logic capacity, and data rate requirements. Our development efforts are guided by such ongoing projects as ultra-wide band (UWB) and multi-channel-multi-antenna (MCMA) radio systems research.

This paper develops a physical channel model for multiple-antenna systems. The model appropriately abstracts the scattering intensity of physical environments, geometry of antenna arrays and degrees of polarization. Then, we use the model to demonstrate that the "space" in wireless systems is composed of three signal dimensions: wavevector, array and polarization. The impact of physical environment, array geometry and polarization are captured separately in the wavevector, array and polarization dimensions respectively. Thus, we solidify the "space" dimensions in complement to the time and frequency dimensions, and unify the available signal space in wireless channels.

We propose a floating-point to fixed-point conversion (FFC) methodology for digital VLSI signal processing systems. The past techniques used to facilitate FFC are first reviewed, followed by a description based on a statistical approach and global optimization which allows a high degree of automation.

A complete OFDM synchronization chain is proposed based on practical synchronization schemes. The synchronization is accomplished in three steps: frame detection (or timing), frequency offset estimation, and phase tracking. For frame detection, time-domain differential PN sequence is used. For frequency offset estimation, time-domain correlation of adjacent pilot symbols estimates the fractional part of the frequency offset and frequency-domain differential PN sequence is used to find the integer part. The phase offset due to frequency offset estimation error as well as the phase noise is tracked using a digital phase lock loop.

The paper proposes an adaptive multiantenna transceiver for narrowband reception. Blind channel tracking algorithms are developed to track the eigen directions of the channel directly instead of the channel itself. Two algorithms are proposed to track the column space of the channel at the receiver, based on the received data. One of the algorithms is free of any division operation, which is more favorable in practice. For the row space of the channel, two approaches are proposed as well. The first approach requires periodic feedback of the demodulated signal from the receiver back to the transmitter where it can make use of its knowledge on the prior transmitted symbols to estimate the row space. In the second approach, the estimation is done at the receiver based on the detected symbols, and the estimated row space is sent back to the transmitter. Adaptive resource allocation is also incorporated into the design.

Every year, the design and EDA communities are besieged by dire warnings about the impending doom of "design as we know it." Every year, another unpleasant physical effect from the evil depths of deep submicron physics surfaces, compromising our designs in new and vile ways. Every year, the same story: more nanometer woes. Rather than endorse a new winner in this year's race for the next worst thing from the nanometer arena, this panel gathers a set of world-class technology experts to debate what effects are hiding just around the next corner, waiting to pounce on the unwary tool or chip designer. Which among these is really the most important, when will it happen, and why.

An interpolation-based maximum likelihood channel estimation scheme using OFDM pilot symbols is proposed. Instead of direct estimation of the frequency response on each subchannel, an interpolation filter is used on the pilot symbols to estimate a smaller set of coefficients that are sufficient to characterize the multipath channel. The actual frequency responses on the subchannels are then computed through inverse filtering of these coefficients. Because the same amount of signal energy is used to estimate a reduced set of unknowns, the estimation accuracy is improved. The scheme is well suited for packet-based OFDM communication systems where pilot symbols instead of pilot tones are usually used at the beginning of each packet for fast synchronization and channel estimation.

This paper presents methods for efficient power minimization at circuit and micro-architectural levels. The potential energy savings are strongly related to the energy profile of a circuit. These savings are obtained by using gate sizing, supply voltage, and threshold voltage optimization, to minimize energy consumption subject to a delay constraint. The true power minimization is achieved when the energy reduction potentials of all tuning variables are balanced. We derive the sensitivity of energy to delay for each of the tuning variables connecting its energy saving potential to the physical properties of the circuit. This helps to develop understanding of optimization performance and identify the most efficient techniques for energy reduction. The optimizations are applied to some examples that span typical circuit topologies including inverter chains, SRAM decoders, and adders. At a delay of 20% larger than the minimum, energy savings of 40% to 70% are possible, indicating that achieving peak performance is expensive in terms of energy. Energy savings of about 50% can be achieved without delay penalty with the balancing of sizes, supplies, and thresholds.

This paper develops a methodology for selecting and optimizing flip-flops for low-energy systems with constant throughput. Characterization metrics, relevant to low-energy systems are discussed, providing insight into timing and energy parameters at both the circuit and system levels. Transistor sizes are optimized for minimal delay under constrained energy consumption. This methodology is applied to characterization of various flip-flop styles and their comparison in 0.25µm CMOS technology under scaled supply voltages. A transmission-gate master-slave latchpair has the largest internal race margin, lowest energy consumption, and has energy-delay product comparable to much faster pulse-triggered latches.

Processors in portable electronic devices generally have a computational load which has time-varying performance requirements. Dynamic Voltage Scaling is a method to vary the processors supply voltage so that it consumes the minimal amount of energy by operating at the minimum performance level required by the active software processes. A dynamically varying supply voltage has implications on the processor circuit design and design flow, but with some minimal constraints it is straightforward to design a processor with this capability.

Microprocessors represent a significant portion of the energy con?sumed in portable electronic devices. Dynamic Voltage Scaling (DVS) allows a device to reduce energy consumption by lowering its processor speed at run-time, allowing a corresponding reduction in processor voltage and energy. A voltage scheduler determines the appropriate operating voltage by analyzing application con?straints and requirements. A complete software implementation, including both applications and the underlying operating system, shows that DVS is effective at reducing the energy consumed with?out requiring extensive software modification.

This paper suggests that since web browsing is an interactive process and downloading a web page can take several seconds to several minutes over slow links, the information presented to the user during this time is important. We present new metrics and visualization techniques to illustrate and quantify web page loading. Given the insight afforded by the metrics, we propose a methodology to improve web access using a new technique, globally progressive interactive web delivery. This technique views the web delivery process as the remote display of a web page and entails applying progressive coding to the document transmission process in its entirety. It also allows the user to explicitly direct link bandwidth to images of interest. This globally progressive interactive framework has been prototyped without modifying either existing web browsers or servers through the use of a web proxy and browser-side Java applets. The framework allows for both protocol and image compression research in a platform-independent manner. Directions of current work on integrating the architecture into existing web infrastructure for greater performance and scalability are discussed.

The performance and computational complexity of five multi-access receivers are compared. A methodology is then presented for making area and power estimates of these algorithms for both software programmable DSP and dedicated direct mapped architectures. With this methodology and by using experimental data from previous designs, the feasibility of implementation of the multi-access receivers can be determined.

Transmitting multimedia data over a code-division multiple access (CDMA) channel presents a new set of challenges: data demands will sometimes exceed the system capacity, in which case the system must make the most efficient use of its limited resources. In this paper, we present our approach for unifying power control, variable forward error correction (VFEC), and scheduling for a downlink system by allocating the system resources. The resources we consider are: fixed bandwidth available for each user and the transmit power budget for each cell. Our objective is to maximize the overall system satisfaction, which we call "system utility." This objective is achieved by applying a distributed algorithm which divides the overall optimization problem into a hierarchy of three levels (system, cell, and user), with each performing independent and parallel optimizations. We perform simulation-based evaluation of the system performance with a simple cell structure and uniformly distributed users. The system is simulated using a specific utility function: the step function. Finally, several practical issues regarding the implementation are investigated.

A new image compression technique, flexible automatic block decomposition (FABD), losslessly compresses typical discrete-tone pseudo-color images 1.5 to 5.5 times more compactly than GIF, and up to twice as compactly as JBIG. The algorithm is designed to exploit the two-dimensional redundancy in an image by expressing the image in terms of itself. Several optimizations allow the algorithm to complete in a matter of seconds on a 100 MIPS processor. Decompression is fast and simple, as is required in a Web browsing environment. Entropy coding techniques result in a coding rate of typically 0.03 bpp-0.20 bpp.

The reduction of energy consumption in microprocessors can be accomplished without impacting the peak performance through the use of dynamic voltage scaling (DVS). This approach varies the processor voltage under software control to meet dynamically varying performance requirements. This paper presents a foundation for the simulation and analysis of DVS algorithms. These algorithms are applied to a benchmark suite specifically targeted for PDA devices.

The architecture of a device that is optimized for wireless information access and display of multimedia data is substantially different than configurations designed for portable stand-alone operation. The requirements to reduce the weight and energy consumption are the same, but the availability of the wireless link, which is needed for the information access, allows utilization of remote resources. A limiting case is when the only computation that is provided in the portable terminal supports the wireless links or the I/O interfaces, and it is this extreme position that is explored in the InfoPad terminal design. The architecture of the InfoPad terminal, therefore, can be viewed as essentially a switch which connects multimedia data sources in the supporting wired network to appropriate InfoPad output devices (e.g., video display), and connects InfoPad input devices to remote processing (e.g., speech recognizer server) in the backbone network.

The InfoPad project was started at UC Berkeley in 1992 to investigatethe issues involved in providing multimedia information accessusing a portable, wireless terminal. It quickly became clear that a keydesign constraint was the energy consumption, which could best beaddressed through an integrated system approach. The project wastherefore organized to address all design levels, including the applicationsand user interface, backbone network protocols, software fordistributed network support, the wireless link, and the pad itselfwhich used a number of low voltage ASIC designs and a processorrunning embedded code. Tools were developed when not available(particularly in support of low energy design), as well as an interfaceto mechanical designers who created a custom injection moldedcase. The wide scope of the project presented a number of uniquechallenges for a research environment and the lessons learn will be presented.

Transmitting multimedia data over a CDMA channel presents a new set of challenges. Sometimes, data demands will exceed the system capacity, in which case the system must make the most efficient use of its limited resources. The resources we consider are: fixed bandwidth available for each user and the transmit power budget for each cell. We present our approach for unifying power control, variable forward error correction (VFEC), and scheduling for allocating the system resources. Our objective is to maximize the overall system satisfaction, which we call "system utility". This objective is achieved by applying a distributed algorithm which divides the overall optimization problem into a hierarchy of three levels (system, cell and user). At each level, the system performs independent and parallel optimizations; the critical information is then passed to the higher level for further optimization. Finally, an iterative and distributed algorithm is applied at the system level to achieve the overall system optimization.

With the popularity of portable devices such as personal digital assistants and personal communicators, as well as with increasing awareness of the economic and environmental costs of power consumption by desktop computers, energy efficiency has emerged as an important issue in the design of electronic systems. While power efficient ASIC's with dedicated architectures have addressed the energy efficiency issue for niche applications such as DSP, much of the computation continues to be implemented as software running on programmable processors such as microprocessors, microcontrollers, and programmable DSP's. Not only is this true for general purpose computation on personal computers and workstations, but also for portable devices, application-specific systems etc. In fact, firmware and embedded software executing on RISC and DSP processor cores that are embedded in ASIC's has emerged as a leading implementation methodology for speech coding, modem functionality, video compression, communication protocol processing etc. This paper describes architectural techniques for energy efficient implementation of programmable computation, particularly focussing on the computation needed in portable devices where event-driven user interfaces, communication protocols, and signal processing play a dominant role. Two key approaches described here are predictive system shutdown and extended voltage scaling. Results indicate that a large reduction in power consumption can be achieved over current day solutions with little or no loss in system performance.

An approach is presented for minimizing power consumption for digital systems implemented in CMOS which involves optimization at all levels of the design. This optimization includes the technology used to implement the digital circuits, the circuit style and topology, the architecture for implementing the circuits and at the highest level the algorithms that are being implemented. The most important technology consideration is the threshold voltage and its control which allows the reduction of supply voltage without significant impact on logic speed. Even further supply reductions can be made by the use of an architecture-based voltage scaling strategy, which uses parallelism and pipelining, to tradeoff silicon area and power reduction. Since energy is only consumed when capacitance is being switched power can be reduced by minimizing this capacitance through operation reduction choice of number representation, exploitation of signal correlations, resynchronization to minimize glitching, logic design, circuit design, and physical design. The low-power techniques that are presented have been applied to the design of a chipset for a portable multimedia terminal that supports pen input, speech I/O and full-motion video. The entire chipset that performs protocol conversion, synchronization, error correction, packetization, buffering, video decompression and D/A conversion operates from a 1.1 V supply and consumes less than 5 mW.>

The increasing demand for portable computing has elevated power consumption to be one of the most critical design parameters. A high-level synthesis system, HYPER-LP, is presented for minimizing power consumption in application specific datapath intensive CMOS circuits using a variety of architectural and computational transformations. The synthesis environment consists of high-level estimation of power consumption, a library of transformation primitives, and heuristic/probabilistic optimization search mechanisms for fast and efficient scanning of the design space. Examples with varying degree of computational complexity and structures are optimized and synthesized using the HYPER-LP system. The results indicate that more than an order of magnitude reduction in power can be achieved over current-day design methodologies while maintaining the system throughput; in some cases this can be accomplished while preserving or reducing the implementation area.>

Modern electronic systems contain a mix of software running on general-purpose programmable processors, algorithms hardwired into dedicated hardware such as custom boards and chips, electromechanical components, and mechanical interconnect and packaging. Far more time Is spent in designing the boards, writing the software to drive, and integrate the hardware, and other such system level issues, than is spent in designing any application-specific ICs that may be needed. Therefore a systems perspective of the design process is essential, as opposed to the conventional "chip-focused" approach. A design framework, called SIERA, for application-specific systems is described in which higher level aspects of system design, including software, multichip design issues present at the board level, and hardware-software integration are addressed, in addition to the design of individual custom chips. A high-level description of the system as a network of processes is mapped to a system architecture template consisting of multiple boards using dedicated hardware modules and ASIC's as well as software processes running on programmable hardware modules. Application of SIERA's design methodology to a multisensory robot control system is also presented.>

An integrated design system for the analysis, design, and implementation of on-chip A/D interfaces using oversampling A/D converters has been developed. The system unifies a diverse base of design knowledge required for mixed analog and digital circuits and covers the design process from specification to mask layout for a variety of configurations. A hierarchical design estimation approach was used to guide system development, allowing designers to quickly estimate performance at a high level of abstraction and to update these estimates as the design progresses. At lower levels of abstraction, architecture templates are used to encapsulate information about particular filter implementations and to simplify the design process. Designers use performance estimates to guide the design process and to make the critical decisions about the choice of algorithm and architecture. Accurate simulation models have been integrated into the design system to allow examination and verification. Results from a 14-b signal acquisition module are presented to illustrate use of the tools and the typical tradeoffs faced at different levels of abstraction. This system illustrates how various design automation techniques can be combined to provide better optimization for a complex system design and to shorten design cycles for custom converters to a matter of days.>

In complex modern day electronic systems, far more time is spent in designing the boards, writing the software to drive and integrate the hardware, and other such system level issues, than is spent in designing any application-specific ICs that may be needed. Unfortunately, most of the research in computer-aided design has been focussed on the more glamorous ASIC design problem, as a result of which the design methodologies and tools at the system level are much more primitive than at the chip level. We have developed a design framework for application-specific systems, called SIERA, that addresses the higher level aspects of system design, including multichip design issues at the board-level, and hardware-software codesign and integration, in addition to the design of individual ASICs. SIERA allows rapid-prototyping of multiboard systems where the functionality is implemented using a mix of dedicated hardware modules and ASICs, as well as software running on programmable hardware modules. A key step in the design methodology provided by SIERA is that of generating the physical implementation of the system hardware from a description of the system architecture. The analogue of this problem at the chip level is referred to as silicon assembly or silicon compilation. In this paper we address this problem at the system level, and describe how the generation and interfacing of board-level modules, board-level physical design, simulation of custom boards, and the overall management of board design are handled in SIERA. While some of the problems could be solved by adapting or extending techniques from the existing ASIC design tools, others required new approaches. Case-studies of several real-life applications are also presented to demonstrate the effectiveness of the board-level physical design methodology embodied in SIERA compared to the traditional PCB design systems.>

The near future will bring the fusion of four rapidly evolving technologies: high speed networking and associated services, wireless communications, scaled integrated circuit technology, and multimedia-based applications. These new technologies will enable the access of multimedia data from network servers at any time and any place by light weight, low cost wireless terminals.

An automated high-level synthesis system, HYPER-LP, for minimizing power consumption in application-specific datapath-intensive CMOS circuits using a variety of architectural and computational transformations is presented. The sources of power consumption are reviewed, and the effects of architectural transformations on the various power components are presented. The synthesis environment consists of high-level estimation of power consumption, a library of transformation primitives (local and global), and heuristic/probabilistic optimization search mechanisms for fast and efficient scanning of the design space. Examples with varying degree of computational complexity and structures are optimized and synthesized. The results indicate that an order of magnitude reduction in power can be achieved over current-day design methodologies while maintaining the system throughput; in some cases, this can be accomplished while preserving or reducing the implementation area.>

A design methodology and high-level synthesis techniques for integrating hardware modules into a system are presented. The interface between modules, which can obey arbitrary protocols, is generated from a high-level specification developed especially for describing intermodule communication. Central to the design methodology are libraries which contain system-level module generators and a strategy to capture the protocol and timing information necessary for interface synthesis. The main impact of this work is raising the interface design abstraction and reducing the effort required from a designer to produce a system using various IC technologies.>

The application of a unified framework for the rapid prototyping of hardware and software for application-specific systems to the development of a real-time multisensor robot control system is described. The key features of the computer-aided system design methodology offered by this framework are exemplified through this system. The system controls, in real-time, a six-degree-of-freedom articulated robot arm using position, force and proximity sensing. Another key aspect of the robot control system is the extensive use of special-purpose dedicated hardware, which provides better performance than systems that are largely based on general-purpose computers.>

An architecture of a dynamically reconfig- urable controller system that can become an IEEE 1149.1 or P1149.2 or P1149.5 master using software is described which provides a low cost, flexible solu- tion for system test and maintenance. Analog and remote testing features are also presented.

A highly integrated VME-based board (based on parallel pipeline projection engine, PPPE, architecture) containing custom VLSI application-specific ICs (ASICs) that implements the forward and inverse Radon transforms in real time has been designed and fabricated. The board contains DSP microcomputers (AT&T DSP32C) that provide the necessary modularity and programming power to support custom Radon-transform ASICs. Parallel and pipelined processing occurs at both the IC and the board level. The ASIC that executes the highly computational- and I/O-intensive forward and inverse Radon transform algorithms has been designed and fabricated in a 1.6-micron scalable CMOS process. It operates at the required 10-MHz video rate, and consists of over 120000 transistors.>

The design of a test controller board for a test support system is presented in this paper. Driven by the SCANTEST software, the test controller board exercises the boundary-scan and scan-path and built-in-self-test hardware implemented on the device under test via a dedicated test-bus. An analog test feature is also described.>

The authors present a CAD (computer-aided design) framework for design of application-specific systems that use a mix of dedicated hardware modules and software processes running on programmable hardware modules. Many application-specific systems are actually being designed using this framework. Some are using the entire top-down mixed hardware-software architecture template based methodology, whereas others are fruitfully employing just the board-level module generators and libraries for specific custom boards. The main contribution of this work is the handling of board-level module generation, system software generation, and hardware-software integration in a unified framework. The application area addressed is that of systems that interact with their environment in real-time; a robot control system and a speech recognition system are examples of such systems.>

Dedicated systems with hardware and software tailored for the application provide tremendous performance improvements over systems based on general-purpose hardware. The authors describe SIERA, a system being developed for rapid-prototyping of the hardware and software components of such dedicated real-time systems starting from a high-level description. Based on their experience of automated generation at the chip level which they developed with the LAGER system, they identify two distinct phases in the design process. The first is the process of mapping the high-level system specification to a set of interacting hardware and software modules. The second is the generation of these software and hardware modules. A mix of mapping, synthesis and library based techniques is being utilized to accomplish these tasks.>

LAGER is an integrated computer-aided design system for algorithm-specific integrated circuit design, targeted at applications such as speech processing, image processing, telecommunications, and robot control. LAGER provides user interfaces at behavioral, structural, and physical levels and allows easy integration of novel CAD tools. LAGER consists of a behavioral mapper and a silicon assembler. The behavioral mapper maps the behavior onto a parameterized structure to produce microcode and parameter values. The silicon assembler then translates the filled-out structural description into a physical layout, and, with the aid of simulation tools, the user can fine tune the data path by iterating this process. The silicon assembler can also be used without the behavioral mapper for high-sample-rate applications. A number of algorithm-specific ICs designed with LAGER have been fabricated and tested, and as examples, a robot arm controller chip and a real-time image segmentation chip are described.>

The authors describe a clock-free design approach that facilitates modular design without compromising global performance. The goal is to support rapid prototyping of real-time digital signal processing systems with a minimum amount of design effort. The approach allows the scaling up of small prototype systems to very large multiboard systems without concern for global timing problems. The authors address the interconnect schemes applicable to real-time systems and the circuit design techniques for a clock-free implementation.>

A system architecture has been developed to implement real-time large-vocabulary continuous-speech recognition using HMM (hidden Markov model) algorithms and bigram language models. It is shown that the largest bottleneck in such a system is located in the memory access. The architecture exploits a variety of techniques, such as partitioning and replication, to cope with this memory bottleneck. The required throughput is achieved with the aid of extensive pipelining (up to thirteen levels deep) and concurrency. The architecture allows extension to larger vocabularies by the addition of more parallel units. Pin count considerations have resulted in the definition of five custom integrated circuits which are currently being tested. Using the proposed approach, the authors are currently designing and debugging a real-time 3000-word continuous-speech recognition system that uses bigram language models.>

The authors construct a processor design approach that does not require the distribution of a clocking signal. To facilitate design of processors that use fully asynchronous components, the first step is to design hazard-free asynchronous interconnection circuits. To this end, a deterministic algorithm was developed to synthesize asynchronous interconnection circuits from high-level specifications. This approach systematically designs correct asynchronous interconnection circuits with the weakest possible constraints and minimal overhead. The authors are primarily concerned with the synthesis of nonmetastable circuits, even though the procedure is also valid of metastable circuit synthesis. The synthesized logic is hazard-free and guaranteed to have the fastest operation according to a behavioral specification. A high-level description is used to specify circuit behavior, not only for a simpler input format, but also as a basis for determining the final optimum designs. Automatic synthesis and the ability to localize the timing considerations reduce design effort when systems become complex.>

Studies performed on a recently developed adaptive control algorithm for high-performance robots have shown that for an effective implementation, hardware must efficiently support I/O and complex decision-making operations. General-purpose digital signal processors, with their emphasis on high-speed arithmetic computations, do not adequately serve the needs of adaptive control and similar applications. As an alternative the authors have generated a custom circuit for a cost-effective implementation of the algorithm. The generation of the custom circuit is based on a customizable digital signal processor embedded inside a CAD framework for application-specific ICs. With this approach, customized versions of the processor are automatically generated from high-level descriptions of algorithms.>

The authors have identified the resolution/decimation tradeoff in practical delta-sigma A/D converters and the add-rate and memory requirements for first-stage decimators, FIR filters can be expressed in a general z-domain structure that scales directly with decimation. A time-domain procedure facilitates computing the effect of practical decimation filters on DSM (delta-sigma modulator) noise, permitting a systematic comparison of electrical performance. Automatically minimized logic networks are an efficient means of realizing compact impulse-response storage to implement these decimators in automatically generated custom IC form.>

Asynchronous processors, which do not require an external clocking signal, give better performance than comparable synchronous processors in situations for which global synchronization with a high-speed clock becomes a limiting factor to system throughput. Automatic synthesis and the ability to decouple the timing considerations from the design of computational blocks make this approach particularly attractive in reducing design effort when systems become complex. A number of issues relevant to asynchronous programmable processors such as interconnection circuit specifications, circuit design, data flow control, program flow control, feedback and initialization, and I/O interface are discussed.>

A real-time video rate histogram processor has been designed, fabricated and tested. A pipelined architecture was chosen to support 10 MHz sample rates. The architecture was then implemented using high-level CAD tools to automate the design. Finally, the fabricated processor was connected to a second chip which implements a programmable look-up table function, to demonstrate real-time histogram equalization of 10 MHz video data.

A set of digital signal processing circuits, generated by the Lager design synthesis system ([PO84], [Ra85], is described. This system maps a behavioral, assembler level description of an algorithm into a set of concurrent operating, customized processors and dedicated i/o circuitry. The nature of this restricted, but flexible target architecture makes it possible to span a large range of applications in the field of speech processing, audio and telecommunications.

We have designed, fabricated and tested several special purpose chips which perform a range of image processing tasks. All operate in real-time (10 MHz for a 512 × 512 image) and require no external storage. Dedicated architectures along with pipelining and parallelism are extensively utilized to achieve real-time performance. This is in contrast to many image processing systems that require large arrays of general purpose processing chips [1] or non-real-time systems that use a single high speed data-path. To demonstrate the use of the circuits, they are being put into a system designed to recognize two-dimensional images (figure 1) that are characterized by their closed contours.

In order to reduce the design time of digital filter bank circuits, a design system has been developed. The software consists of the filter compiler which converts high level filter descriptions to hardware descriptions and the layout generator which converts the hardware descriptions to a layout file. To verify the algorithms before fabrication, a test system is employed. The development time of this system was kept to a minimum by designing the hardware to be easily micro coded and assembled. Several circuits have been fabricated and tested that were generated with this system, including a single bandpass filter chip, a 112-pole 16-channel filter bank for a speech recognition system and a 16-channel spectrum analyzer for consumer stereo applications. The speech recognition chip achieved a SNR of 80 dB with an area of 25 mm /sup 2/ in a 4-micron NMOS technology.

An integrated CAD system for the automated design of digital signal-processing (DSP) circuits for audio and telecommunication applications is described. The system uses as unique input a symbolic description of algorithm. This representation is translated into an actual layout using a two-step process. First, the symbolic input is mapped into the target architecture, which consists basically of a set of concurrent processors and dedicated I/O circuitry. The resulting hardware configuration is compiled into a layout description through a full exploitation of the hierarchy and the modularity of the architecture, calling consecutively a tiler, a floorplanner, and a global placement and routing tool. All these layout generation tools are able to support a wide range of technologies. The provision of a dedicated register transfer level simulator allows for the efficient debugging and algorithmic checking of the real-time operating signal-processing algorithms. The efficiency and the usefulness of this design methodology has been demonstrated by multiple examples. Experiments have shown that the use of these techniques can reduce the complete design process to a few months.

The root LPC system has closed form analysis and formant like synthesis structure. By using quadratic coefficient quantization and section repeat its data rate can be lower than 1Kbps. By including representative residual signal of variable repetition rate its quality can be continuously improved. A special purpose NMOS-LSI chip was built to implement the synthesis function.

Dynamic time warping is considered a superior way to perform time alignment in speech recognition. [1] Unfortunately dynamic programming algorithms require too much computation for conventional computer architectures to handle and still provide good response time with 1000 reference words. This paper presents a single chip that is capable of the performing the dynamic time warp processing necessary for recognizing 1000 words in real-time.

An approach for implementing a widely used parallel processing pitch extraction algorithm is described which can be implemented with one custom MOS-LSI integrated circuit along with an inexpensive single chip microprocessor. This reduction in hardware (and therefore cost and power) over previous techniques is made possible by the careful partitioning of the computation between analog and digital circuitry which can both be integrated onto the same IC. A breadboard which simulates the MOS integrated circuit has been built and interfaced to the microprocessor. The complete system demonstrates that excellent performance can be obtained using this approach.