An extremely dense high-speed serial interface validation tester is presented. By relying on parallelism and on efficient measurement techniques, the proposed tester significantly reduces the time to validate the key parameters for serdes interfaces such as the bit error rate, receiver sensitivity, receiver jitter tolerance, and transmit jitter generation. Key timing specifications include periodic jitter injection with less than 5 psec edge-placement resolution and jitter measurement with 160 fsec sampling delay resolution

Summary form only given. In fact, contemporary analog test seems to represent a niche area for which solutions are always future ones. Yet, analog circuits are being mass-produced at astounding rates (whether within more complex digital IC's or as purely analog parts). This apparent paradox is addressed in this panel, which adopts a problem-solving approach to defining and addressing the analog test domain. It is the panel's position that the very definition of everything "analog" has shifted in recent years, and a significant dichotomy between test practitioners and chip manufacturers on the one hand and DFT-providers or researchers on the other exists. In this context, a typical question may be: is DFT or BIST really the answer, or should the research community focus more on test techniques? As it turns out, the industry is indeed going through a rapid change that is impacting everything from test engineers to test equipment and business models. This, coupled with little investment in the way of analog options in test equipment, is one of the many reasons there is a "problem" in analog testability.

A novel and efficient method is presented for computing the delay and supply current pulse in a CMOS inverter with an RC load. The method builds on existing techniques for computing these quantities in the presence of a capacitance load. As in the work of other authors, the concept of an effective capacitance C/sub eff/ is used. However, here it captures the inverter's behavior only while the charging/discharging transistor is in saturation and, therefore, behaves like a current source to a good approximation. This capacitance is determined by means of a simple iterative procedure that uses an empirical piecewise-linear approximation to the RC circuit's output voltage, which has a normal CMOS symmetrical form. Since a C/sub eff/ defined in the above way is independent of the inverter's parameters, such as transistor size, the coefficients of the approximation have to be determined for only one reference inverter. A simple analytical method yields the inverter's output voltage outside the saturation region. The complete model has been shown to be accurate for both 0.8-/spl mu/m 5-V and 0.24-/spl mu/m 2.5-V CMOS technologies. Its speed is comparable to that of the "capacitance load" techniques that it relies on.