We present a throughput-driven partitioning algorithm and a throughput-preserving merging algorithm for the high-level physical synthesis of latency-insensitive (LI) systems. These two algorithms are integrated along with a published floorplanner [5] in a new iterative physical synthesis flow to optimize system throughput and reduce area occupation. The partitioning algorithm performs bottom-up clustering of the internal logic of a given IP core to divide it into smaller ones, each of which has no combinational path from input to output and thus is legal for LI-interface encapsulation. Applying this algorithm to cores on critical feedback loops optimizes their length and in turn enables throughput optimization via the subsequent floorplanning. The merging algorithm reduces the number of cores on non-critical loops, lowering the overall area taken by LI interfaces without hurting the system throughput. Experimental results on a large system-on-chip design show a 16.7% speedup in system throughput and a 2.1% reduction in area occupation.

Synchronous languages are well suited to implementation and verification of reactive systems. Large reactive systems tend to be distributed to cope with scalability and application specific demands. We propose abstractions for distributed reactive systems modelled as a set of synchronous nodes with asynchronous communication between them. The special features of synchronous programs allow us to obtain abstractions that are also valid synchronous programs only by syntactic transformations. For a given program, the set of all such abstractions forms a semi-lattice with the original program as the bottom and the most abstract program as the top element. The transformation we define is a natural basis for constructing an abstraction-refinement framework for verification. Given a program and a safety property, the abstraction-refinement process is a search in a lattice of programs obtained via syntactic transformations. We have implemented this abstraction refinement framework in a prototype tool and report our case studies.

With the arrival of nanometer technologies wire delays are no longer negligible with respect to gate delays, and timing-closure becomes a major challenge to system-on-chip designers. Latency-insensitive design (LID) has been proposed as a "correct-by-construction" design methodology to cope with this problem. In this paper we present the design and implementation of a new class of interface circuits to support LID that offers substantial performance improvements with limited area overhead with respect to previous designs proposed in the literature. This claim is supported by the experimental results that we obtained completing semi-custom implementations of the three designs with a 90 nm industrial standard-cell library. We also report on the formal verification of our design: using the NuSMV model checker we verified that the RTL synthesizable implementations of our LID interface circuits (relay stations and shells) are correct refinements of the corresponding abstract specifications according to the theory of LID.