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Sujaya Srinivasan

dblp:53/7791 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2000
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Distributed systems · 28% Parallel and multicore computing · 28% Memory systems · 28%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
direct memory access
0.012000
High Speed Hardware-Assisted Real-Time Interprocess Communication for Embedded Microcontrollers · RTSS 2000
Parallel and multicore computing
hardware-assisted IPC
0.012000
High Speed Hardware-Assisted Real-Time Interprocess Communication for Embedded Microcontrollers · RTSS 2000
Distributed systems › operating system support
interprocess communication
0.012000
High Speed Hardware-Assisted Real-Time Interprocess Communication for Embedded Microcontrollers · RTSS 2000
Embedded and real-time systems
cyber-physical system platforms
0.012000
High Speed Hardware-Assisted Real-Time Interprocess Communication for Embedded Microcontrollers · RTSS 2000
Embedded and real-time systems › control systems
digital control systems
0.012000
High Speed Hardware-Assisted Real-Time Interprocess Communication for Embedded Microcontrollers · RTSS 2000

Methods — techniques the papers use, named apart from their topics

port automaton model · 0.0direct memory access · 0.0
YearPublicationVenuePosition
2000 High Speed Hardware-Assisted Real-Time Interprocess Communication for Embedded Microcontrollers
abstract
We have designed a hardware-assisted interprocessor communication (IPC) mechanism that can reduce the communication overhead of embedded microcontrollers by a factor of 30 or more. The real-time communication mechanism allows processes to exchange data in a predictable and timely manner, with minimum overhead, in both single and multiprocessor environments. The hardware assist is a modified DMA (direct memory access) architecture. We combined it with an existing software-based real-time communication mechanism that takes advantage of the fact that, in control systems, IPC requirements for most processes in the system are small and known a priori. The mechanism is designed especially for digital control systems that can be defined as a collection of software components that follow the port automaton model, for which it is more important to always obtain the most recent data, rather than always needing to process every data item.
Sujaya Srinivasan, David B. Stewart
RTSS1