Demo Data from VLDB 2026 / reviewers in the wild / expert
Jinpeng Lv
dblp:54/11157
· DBLP profile ↗
4ranked-venue papers
3as first author
0since 2021 · last 2018
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 first-authorSecurity and privacy · 1Software engineering, systems software and programming languages · 1 · 1 first-authorGraphics, computer vision, multimedia, augmented reality and games · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware verification and test › functional verification › logic verification
arithmetic circuit verification |
0.2 | 1 | 2013 | Efficient Gröbner Basis Reductions for Formal Verification of Galois Field Arithmetic Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2013 |
Electronic design automation › hardware verification and test
formal verification |
0.2 | 1 | 2013 | Efficient Gröbner Basis Reductions for Formal Verification of Galois Field Arithmetic Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2013 |
Electronic design automation › hardware verification and test › formal verification
galois field arithmetic circuit verification |
0.2 | 1 | 2013 | Efficient Gröbner Basis Reductions for Formal Verification of Galois Field Arithmetic Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2013 |
Electronic design automation › hardware verification and test
hardware verification |
0.2 | 1 | 2013 | Efficient Gröbner Basis Reductions for Formal Verification of Galois Field Arithmetic Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2013 |
Methods — techniques the papers use, named apart from their topics
polynomial division · 0.2gröbner basis · 0.2gaussian elimination · 0.2f4 algorithm · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2018 | A novel auxiliary data construction scheme for reversible data hiding in JPEG images
Jinpeng Lv, Sheng Li 0006, Xinpeng Zhang 0001 |
Multim. Tools Appl. | 1 |
| 2016 | Distortion Function for Spatial Image Steganography Based on the Polarity of Embedding Change
Zichi Wang, Jinpeng Lv, Qingde Wei, Xinpeng Zhang 0001 |
IWDW | 2 |
| 2013 | Efficient Gröbner Basis Reductions for Formal Verification of Galois Field Arithmetic CircuitsabstractGalois field arithmetic is a critical component in communication and security-related hardware, requiring dedicated arithmetic architectures for better performance. In many Galois field applications, such as cryptography, the data-path size in the circuits can be very large. Formal verification of such circuits is beyond the capabilities of contemporary verification techniques. This paper addresses formal verification of combinational arithmetic circuits over Galois fields of the type${\BBF}_{2^{k}}$using a computer-algebra/algebraic-geometry-based approach. The verification problem is formulated as membership testing of a given specification polynomial in a corresponding ideal generated by the circuit constraints. Ideal membership testing requires the computation of a Gröbner basis, which is computationally very expensive. To overcome this limitation, we analyze the circuit topology and derive a term order to represent the polynomials. Subsequently, using the theory of Gröbner bases over${\BBF}_{2^{k}}$, we show that this term order renders the set of polynomials itself a minimal Gröbner basis of this ideal. Consequently, the verification test reduces to a much simpler case of Gröbner basis reduction via polynomial division, significantly enhancing verification efficiency. To further improve our approach, we exploit the concepts presented in the$F4$algorithm for Gröbner basis, and show that the verification test can be formulated as Gaussian elimination on a matrix representation of the problem. Finally, we demonstrate the ability of our approach to verify the correctness of, and detect bugs in, up to 163-bit circuits in${\BBF}_{2^{163}}$—whereas verification utilizing contemporary techniques proves infeasible. Jinpeng Lv, Priyank Kalla, Florian Enescu |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 2012 | Efficient Gröbner basis reductions for formal verification of galois field multipliersabstractGalois field arithmetic finds application in many areas, such as cryptography, error correction codes, signal processing, etc. Multiplication lies at the core of most Galois field computations. This paper addresses the problem of formal verification of hardware implementations of (modulo) multipliers over Galois fields of the type F(2k), using a computer-algebra/algebraic-geometry based approach. The multiplier circuit is modeled as a polynomial system in F(2k)[x1, x2, ... , xd] and the verification problem is formulated as a membership test in a corresponding (radical) ideal. This requires the computation of a Gröbner basis, which can be computationally intensive. To overcome this limitation, we analyze the circuit topology and derive a term order to represent the polynomials. Subsequently, using the theory of Gröbner bases over Galois fields, we prove that this term order renders the set of polynomials itself a Gröbner basis of this ideal - thus significantly improving verification. Using our approach, we can verify the correctness of, and detect bugs in, upto 163-bit circuits in F(2163); whereas contemporary approaches are infeasible. Jinpeng Lv, Priyank Kalla, Florian Enescu |
DATE | 1 |