The use of a wake-up receiver (WUR) is an attractive means to reduce power consumption. However, when the wake-up signal (WUS) is sent in-band, the use of a WUR may potentially reduce the spectrum efficiency of the system. In this paper, we propose to multiplex the WUS, based on ON-OFF keying, with the user data using FDMA or OFDMA to allow for spectrum efficient use of WURs. The proposed WUR architecture is based on an envelope detector and an uncertain intermediate frequency (IF), which means that the user data will act as interference for the WUS. In spite of its low complexity, it is shown by means of simulations that good sensitivity performance can still be obtained. In addition, the multiplexing allows for great flexibility and the power allocated to the WUS and the user data, respectively, can be selected based on actual requirements.

This work presents a 1.8-GHz VCO tuned by a pMOS capacitor working exclusively in the accumulation and depletion regions. The VCO has been fabricated in a standard 0.6 /spl mu/m CMOS process. It shows a tuning range of about 11% and a phase noise of -137 dBc/Hz at 3 MHz offset from the carrier, for a current consumption of 2.7 mA. The VCO compares favorably with a CMOS VCO tuned by a reverse biased diode varactor.

In this paper, we review the Bluetooth technology, a new universal radio interface enabling electronic devices to connect and communicate wirelessly via short-range connections. Motivations for the radio requirements are given, and the implications of system parameters like operating modes, frequency hopping, interference resistance are discussed from a low-power perspective. Speci!c characteristics enabling low-cost single-chip implementations and supporting low power consumption are outlined.

In the past decades, progress in microelectronics and VLSI technology has fostered the widespread use of computing and communication applications in portable electronic devices. In this paper, we review the Bluetooth technology, a new universal radio interface enabling electronic devices to connect and communicate wirelessly via short-range connections. Motivations for the air interface design and radio requirement decisions are discussed. Frequency hopping, interference resistance, and the concepts of ad hoc connectivity and scatternets are explained in detail. Furthermore, Bluetooth characteristics enabling low-cost single-chip implementations and supporting low power consumption are discussed.

Power dissipation can be addressed at three different levels: system, architecture, and circuit.The system has to be designed to allow for efficient paging to allow the phone to sleep for long period, and the access scheme and modulation method have a large impact on circuit performance.A proper architecture and circuit partitioning has to be chosen: offchip devices offer lower current consumption, but signal routing may require high power levels.At the circuit level, optimized supply voltages and power-down modes are important for digital circuits.Dynamic-bias analog circuits may adapt to the signal and interference situation.

This short paper presents a method that makes it possible to analyze switched-capacitor (SC) networks in discrete time using compacted nodal analysis in continuous time. Our objective is to perform time-discrete analysis in the z-domain using any symbolic analysis tool (e.g. CASCA) intended for analysis of time-continuous networks in the s-domain. A new equivalent analog circuit is used to describe the switched capacitors in the s-domain with z=s instead of z=e/sup sT/ which gives a simple translation between the two domains. Two SC examples are considered: an inverting amplifier and a biquad.

This paper describes the implementation of a switch-level model in a waveform-relaxation-based concurrent circuit simulator. The model requires much less time for model evaluation compared to continuous models, while still giving sufficient accuracy. Multicomputer runs have shown speedups in the range from 5 to 10, corresponding to efficiencies between 15 and 30%; more than 100 computing nodes have been efficiently used, with less than 4 circuit nodes per computing node.>