Zero-watermarking techniques constructs zero watermarks without modifying the original host audio signal. This paper presents a robust zero-watermarking algorithm for stereo audio signals. The proposed algorithm exploits inter-channel redundancy of stereo audio signal in order to construct zero watermarks binary sequence. Here, the features are extracted from DWTDCT-SVD domain to construct zero watermarks; and are found to be robust against modified discrete cosine transform (MDCT)-based perceptual stereo audio coding schemes. Extensive experimental results assure that the proposed watermarking scheme is highly secure as well as robust to common attacks like, MP3 compression, cropping, filtering, re-sampling, amplitude scaling and re-quantisation, etc. To the best of our knowledge, zero-watermarking algorithm based on stereo audio properties is proposed first time.

The steganography is used for secure communication. In this paper we propose Dual Tree Complex Wavelet Transform (DTCWT) based high capacity steganography using coefficient replacement and adaptive scaling. The DTCWT is applied on cover image and Lifting Wavelet Transform2 (LWT2) is applied on payload to convert spatial domain into transform domain. The new concept of replacing HH sub band coefficients of DTCWT of cover image by LL sub band coefficients of payload is introduced to generate intermediate stego object. The adaptive scaling factor is used based on entropy of cover image to scale down intermediate stego object coefficient values to generate final stego object. It is observed that the capacity and security are increased in the proposed algorithm compared to existing algorithms.

The face recognition is an efficient biometric system to identify a person. In this paper, we propose Face Recognition using Transform Domain Texture Features (FRTDTF). The face images are preprocessed and two sets of texture features are extracted. In first feature set, the Discrete Wavelet Transform (DWT) is applied on face image and considered only high frequency sub band coefficients to extract edge information efficiently. The Dual Tree Complex Wavelet Transform (DTCWT) is applied on high frequency sub bands of DWT to derive Low and High frequency DTCWT coefficients. The texture features of DTCWT coefficients are computed using Overlapping Local Binary Pattern (OLBP) to generate feature set 1. In second feature set, the DTCWT is applied on preprocessed face image and considered all frequency sub bands coefficients to extract significant information and edge information of face image. The texture features of DTCWT matrix are computed using OLBP to generate feature set 2. The final feature set is the concatenation of feature set 1 and set 2. The Euclidian distance (ED) is used to compare test image features with features of face images in the database. It is observed that, the performance parameter values are better in the case of proposed algorithm compared to existing algorithms.

The optimization of queries is critical in database management systems and the complexity involved in finding optimal solutions has led to the development of heuristic approaches. Answering data mining query involves a random search over large databases. Due to the enormity of the data set involved, model simplification is necessary for quick answering of data mining queries. In this paper, we propose a hybrid model using rough sets and genetic algorithms for fast and efficient query answering. Rough sets are used to classify and summarize the datasets, whereas genetic algorithms are used for answering association related queries and feedback for adaptive classification. Here, we consider three types of queries, i.e., select, aggregate and classification based data mining queries. Summary tables that are built using rough sets and analytical model of attributes are used to speed up select queries. Mining associations, building concept hierarchies and reinforcement of reducts are achieved through genetic algorithms. The experiments are conducted on three real-life data sets, which include KDD 99 Cup data, Forest Cover-type data and Iris data. The performance of the proposed algorithm is analyzed for both execution time and classification accuracy and the results obtained are good

In analog testing, usage of a single sinusoid as a test signal when compared to multitone signal, and fault detection with digital counting technique, facilitate the test implementation with simple built-in self-test hardware and make testing more cost effective. In this paper, a novel test-set-selection technique known as ExpoTan for testing linear-time-invariant (LTI) circuits is presented. The authors formulate the test generation problem with tan-1( ) and exponential functions for identification of a test signal with maximum fault coverage. For identification of a test signal the ExpoTan technique combines test generation and test-set-compaction tasks in a single phase and generates an efficient compacted test set. The experimental results show that the testing of LTI circuits using ExpoTan technique for the benchmark circuits achieves the required fault coverage with shorter testing time and test generation time

Mammography is a medical imaging technique that combines, low-dose radiation and high-contrast, high-resolution film for examination of the breast and screening for breast cancer. This paper proposes a random forest decision classifier (RFDC) for classifying mammograms. Results of screening the mammograms are organised by classification and finally grouped into three categories i.e., normal, cancerous and benign. Experimental results show that this method performs well with the classification accuracy reaching nearly 90% in comparison with the already existing algorithms

Distributed power control schemes are extensively employed in the cellular networks and are capable of improving the capacity of the network. However, the power control schemes from the cellular networks suffer from performance degradation due to self and direct-interference and hidden-terminal problems when directly employed in ad hoc networks. Most of the existing channel reservation-based power control protocols for ad hoc networks employ incremental power allocation rather than global allocation of the power to the incoming links; thus, they may not effectively utilize the spatial frequency reuse in the network. This paper presents a distributed channel access protocol that couples the channel reservation and the iterative/global transmission power control schemes in ad hoc networks. The designed protocol considers the convergence problem of the global power control in ad hoc networks. The designed access criteria employ the local admission control based on the sufficient criteria for admissibility and global power control for balancing the SIR (signal to interference ratio) of the links. In the performance evaluation study of the designed protocol, an almost twofold increase in the throughput and capacity is observed compared to the existing power-controlled protocol for ad hoc networks.

The XML technology, with its self-describing and extensible tags, is significantly contributing to the next generation semantic web. The present search techniques used for HTML and text documents are not efficient when retrieving relevant XML documents. In this paper, Self Adaptive Genetic Algorithms are presented to learn about the tags, which are useful in indexing. The indices and relationship strength metric are used to extract fast and accurate semantically related elements in the XML documents. The Experiments are conducted on the DataBase systems and Logic Programming (DBLP) XML corpus and are evaluated for precision and recall. The proposed SAGAXsearch outperforms XSEarch3 and XRank20 with respect to accuracy and query execution time.

A new test-set selection technique based on the frequency-domain testing of analog circuits is presented in this paper. We propose a new automatic test pattern generation (ATPG) method known as MultiDetect for testing linear time invariant (LTI) circuits. The proposed technique is best suited for use of existing building blocks in systems-on-chip for implementation of an on-chip test-signal generator and test-response analyzer. The generated test set with the MultiDetect method can effectively detect and diagnose both soft and hard faults and does not require any precision analog signal sources or signal measurement circuits when implemented as built-in self-test (BIST). Testing of analog blocks based on circuit-transfer function makes our ATPG a general purpose method for all kinds of LTI circuits. A new novel test method causing the device under test to saturate or get out of saturation, to detect a fault with simple detection hardware, is also introduced in this paper. In our proposed novel test scheme, usage of a single sinusoid as a test signal when compared to multitone signal, and detection of faults with digital counting technique, facilitate the test implementation with simple BIST hardware and make testing more cost effective. The sinusoid is a very useful waveform for testing and analyzing LTI circuits. In the steady state, both the input and output of a stable LTI circuit are sinusoids of the same frequency. The relationship between the amplitudes and phase angles of the input and output sinusoids is frequency-dependent. Identification of a sinusoid that detects more faults results in an optimized test signal set. The technique used in the MultiDetect method for identification of a sinusoid results in an efficient compacted test set. The search for fault diagnosis is restricted to a limited set of faults, making diagnosis fast in the MultiDetect method. A methodology for test-set compaction of the MultiDetect technique is described and results of experiments on various test circuits are discussed. The proposed method is seen to be efficient for low-power applications. The experimental results show that the testing of LTI circuits using the MultiDetect technique for the benchmark circuits achieves the required fault coverage with much shorter testing time.

We propose a novel evolutionary approach to the problem of timing-driven FPGA placement. The method used is evolutionary programming (EP) with incremental position encoded in the population. This uses considerably less memory compared to a method with direct position-encoding for members of the population. The algorithm has been implemented in C++, and the results on MCNC benchmark circuits are presented. The results are superior to those obtained using conventional Simulated Annealing (SA) based approach. The results of an EP-SA approach using the proposed evolutionary programming method are also presented.

Explores the feasibility of applying genetic programming (GP) to multicategory pattern classification problem. GP can discover relationships and express them mathematically. GP-based techniques have an advantage over statistical methods because they are distribution-free, i.e., no prior knowledge is needed about the statistical distribution of the data. GP also automatically discovers the discriminant features for a class. GP has been applied for two-category classification. A methodology for GP-based n-class classification is developed. The problem is modeled as n two-class problems, and a genetic programming classifier expression (GPCE) is evolved as a discriminant function for each class. The GPCE is trained to recognize samples belonging to its own class and reject others. A strength of association (SA) measure is computed for each GPCE to indicate the degree to which it can recognize samples of its own class. SA is used for uniquely assigning a class to an input feature vector. Heuristic rules are used to prevent a GPCE with a higher SA from swamping one with a lower SA. Experimental results are presented to demonstrate the applicability of GP for multicategory classification, and they are found to be satisfactory. We also discuss the various issues that arise in our approach to GP-based classification, such as the creation of training sets, the role of incremental learning, and the choice of function set in the evolution of GPCE, as well as conflict resolution for uniquely assigning a class.

We propose a new coverage metric for delay fault tests. The coverage is measured for each line with a rising and a falling transition, but the test criterion differs from that of the slow-to-rise and slow-to-fall transition faults. A line is tested by a line delay test, which is a robust path delay test for the longest sensitizable path producing a given transition on the target line. Thus, the test criterion resembles path delay test and not the gate or transition delay test. Yet, the maximum number of tests (or faults) is limited to twice the number of lines. In a two-pass test-generation procedure, we first attempt delay tests for a minimal set of longest paths for all lines. Fault simulation is used to determine the coverage metric. For uncovered lines, in the second pass, several paths of decreasing lengths are targeted. We give results for several benchmark circuits.

Genetic algorithms (GAs) are efficient and robust search methods that are being employed in a plethora of applications with extremely large search spaces. The directed search mechanism employed in GAs performs a simultaneous and balanced exploration of new regions in the search space and exploitation of already-discovered regions. This paper introduces the notion of fitness moments for analyzing the working of GAs. We show that the fitness moments in any generation may be predicted from those of the initial population. Since a knowledge of the fitness moments allows us to estimate the fitness distribution of strings, this approach provides for a method of characterizing the dynamics of GAs. In particular, the average fitness and fitness variance of the population in any generation may be predicted. We introduce the technique of fitness-based disruption of solutions for improving the performance of GAs. Using fitness moments, we demonstrate the advantages of using fitness-based disruption. We also present experimental results comparing the performance of a standard GA and two other GAs (the controlled disruption GA and the adaptive GA) that incorporate the principle of fitness-based disruption. The experimental evidence clearly demonstrates the power of fitness-based disruption.

Various Artificial Neural Networks (ANNs) have been proposed in recent years to mimic the human brain in solving problems involving human-like intelligence. Efficient mapping of ANNs comprising of large number of neurons onto various distributed MIMD architectures is discussed in this paper. The massive interconnection among neurons demands a communication efficient architecture. Issues related to the suitability of MIMD architectures for simulating neural networks are discussed. Performance analysis of ring, torus, binary tree, hypercube, and extended hypercube for simulating artificial neural networks is presented. Our studies reveal that the performance of the extended hypercube is better than those of ring, torus, binary tree, and hypercube topologies.

We discuss a novel model for analyzing the working of Genetic Algorithms (GAs), when the objective function is a function of unitation. The model is exact (not approximate), and is valid for infinite populations. Functions of unitation depend only on the number of 1's in any string. Hence, we only need to model the variations in the distribution of strings with respect to the number of 1's in the strings. We introduce the notion of a Binomial Distributed Population (BDP) as the building block of our model, and we show that the effect of uniform crossover on BDPs is to generate two other BDPs. We demonstrate that a population with any general distribution may be decomposed into several BDPs. We also show that a general multipoint crossover may be considered as a composition of several uniform crossovers. Based on these results, the effects of mutation and crossover on the distribution of strings have been characterized, and the model has been defined. GASIM-a Genetic Algorithm Simulator for functions of unitation-has been implemented based on the model, and the exactness of the results obtained from GASIM has been verified using actual Genetic Algorithm runs. The time complexity of the GA simulator derived from the model is O(l(3)) (where l is the string length), a significant improvement over previous models with exponential time complexities.

We present a novel genetic algorithm-based partitioning scheme for multichip modules (MCM's) which integrates four performance constraints simultaneously: pin count, area, heat dissipation, and timing. We also present a similar partitioning algorithm based on evolutionary programming. Experimental studies demonstrate the superiority of these methods over deterministic Fiduccia-Mattheyes (FM) algorithm and simulated annealing (SA) technique. Our approach performs better than another genetic algorithm-based method recently reported. The adaptive change of crossover and mutation probabilities results in better convergence of the partitioning algorithm.

We describe the design of a directory-based shared memory architecture on a hierarchical network of hypercubes. The distributed directory scheme comprises two separate hierarchical networks for handling cache requests and transfers. Further, the scheme assumes a single address space and each processing element views the entire network as contiguous memory space. The size of individual directories stored at each node of the network remains constant throughout the network. Although the size of the directory increases with the network size, the architecture is scalable. The results of the analytical studies demonstrate superior performance characteristics of our scheme compared with those of other schemes.

The electrocardiogram (ECG), which represents the electrical activity of the heart, is widely used for the diagnosis of cardiac diseases. The ECG typically consists of three important component waves, called the P, QRS, and T waves, which provide clinical information about the functioning of the heart. An important problem in ECG signal processing is that of delineation of the ECG component waves. The delineation of the P wave is difficult in certain cardiac diseases where the P wave overlaps the other ECG component waves. We present an innovative algorithm, for the delineation of the P waves, which works well even in such cases. The algorithm basically consists of pole-zero modeling of the discrete cosine transformed ECG. The resulting pole-zero filter is then decomposed into a set of unique partial fractions (PF), with each PF representing a sub-component or a fractional component (FC) of the ECG. A pole angle template matching procedure is used to identify the PFs of the QRS and T waves, and then their corresponding FCs are subtracted from the ECG to leave the P wave as the residue.>

In this paper we describe an efficient approach for multimodal function optimization using genetic algorithms (GAs). We recommend the use of adaptive probabilities of crossover and mutation to realize the twin goals of maintaining diversity in the population and sustaining the, convergence capacity of the GA. In the adaptive genetic algorithm (AGA), the probabilities of crossover and mutation, p/sub c/ and p/sub m/, are varied depending on the fitness values of the solutions. High-fitness solutions are 'protected', while solutions with subaverage fitnesses are totally disrupted. By using adaptively varying p/sub c/ and p/sub ,/ we also provide a solution to the problem of deciding the optimal values of p/sub c/ and p/sub m/, i.e., p/sub c/ and p/sub m/ need not be specified at all. The AGA is compared with previous approaches for adapting operator probabilities in genetic algorithms. The Schema theorem is derived for the AGA, and the working of the AGA is analyzed. We compare the performance of the AGA with that of the standard GA (SGA) in optimizing several nontrivial multimodal functions with varying degrees of complexity.>

In this paper, we propose a new channel routing algorithm based on genetic approach. This involves designing a new encoding scheme and an evaluation function used by the genetic algorithm (GA) for channel routing problem. The algorithm has been implemented as both sequential and distributed CA. The speedup achieved is positive and encouraging.

In this paper we propose a novel technique to model and analyze the performability of parallel and distributed architectures using GSPN-reward models.

Inspite of numerous research advancements made in recent years in the area of formal techniques, specification of real-time systems is still proving to be a very challenging and difficult problem. In this context, this paper critically examines state-of-the-art specification techniques for real-time systems and analyzes the emerging trends.

Increase in the complexity of VLSI digital circuit design demands faster logic simulation techniques than those currently available. One of the ways of speeding up existing logic simulation algorithms is by exploiting the inherent parallelism in the sequential version. The authors explore the possibility of mapping a T-algorithm based logic simulation algorithm onto a cluster of workstations interconnected by an Ethernet. The set of gates at a particular level is partitioned by the master task (running on the host processor) among the slave tasks (running on the other processors). Each slave task evaluates the set of gates assigned to it, for the complete simulation period independent of other slave tasks and communicates the evaluated outputs to the master task. After receiving the evaluated output from all the slaves, the master task partitions the gates at the next level and communicates this new set of gates to the slave tasks. The above process is repeated for all the levels in the circuit. The details of the partitioning scheme and its performance are also discussed.>

A new interconnection topology-the extended hypercube-consisting of an interconnection network of k-cubes is discussed. The extended hypercube is a hierarchical, expansive, recursive structure with a constant predefined building block. The extended hypercube retains the positive features of the k-cube at different levels of hierarchy and at the same time has some additional advantages like reduced diameter and constant degree of a node. The paper presents an introduction to the topology of the extended hypercube and analyzes its architectural potential in terms of message routing and executing a class of highly parallel algorithms. Topological properties and performance studies of the extended hypercube are presented.>

The authors present a parallel algorithm for logic simulation of VLSI circuits. It is implemented on a network of transputers connected in a ring topology. The approach is based on partitioning a functionality matrix representation of the circuit among the transputers and adopting a data flow technique for the solution. A significant aspect of the algorithm is that it overlaps computation with communication, thereby reducing the communication overhead. It also attempts even distribution of load in order to reduce processor idle time. The algorithm possesses the advantages of ease of implementation and ease of extension to incorporate additional parameters for simulation. Performance results of the algorithm are given.>

Implementation details of efficient schemes for lenient execution and concurrent execution of re-entrant routines in a data flow model have been discussed in this paper. The proposed schemes require no extra hardware support and utilise the existing hardware resources such as the Matching Unit and Memory Network Interface, effectively to achieve the above mentioned goals.

Two types of organizations are presented for frame buffers of m*m pixels: one is a single wavefront complex cell array requiring O(m/sup 2/n) space and the other is a simple cell multiple wavefront array with O(m/sup 2/) area and O(n/sup 2/) wavefronts. Both these organizations have two main advantages over an earlier method: the cells and the interconnection among them are regular and hence are suitable for efficient VLSI implementation, and the organization permits evaluation of higher-order polynomials.>

In this paper, we propose a systolic architecture for hidden-surface removal. Systolic architecture is a kind of parallel architecture best known for its easy VLSI implementability. After discussing the design details of the architecture, we present the results of the simulation experiments conducted in order to evaluate the performance of the architecture.

This paper deals with the development and performance evaluation of three modified versions of a scheme proposed for medium access control in local area networks. The original scheme implements a collision-free and fair medium arbitration by using a control wire in conjunction with a data bus. The modifications suggested in this paper are intended to realize the multiple priority function in local area networks.

Abstract In Computer‐Aided Design applications there is often a need to compute the union, intersection and Merence of two polygons or polyhedra. The sequential algorithms for this problem are characterized by poor speed of response and large computational complexity. In order to remove these defects, an algorithm amenable to implementation on a parallel architecture is proposed. The parallel architecture designed is a systolic one which forms a dedicated subsystem to perform set‐theoretic operations on polygons. The improvement in speed gained by using the systolic array as compared to a uniprocessor has been evaluated using simulation techniques. Extensions of this architecture to perform the same operations on polyhedra are also discussed.

A new language concept for high-level distributed programming is proposed. Programs are organised as a collection of concurrently executing processes. Some of these processes, referred to as liaison processes, have a monitor-like structure and contain ports which may be invoked by other processes for the purposes of synchronisation and communication. Synchronisation is achieved by conditional activation of ports and also through port control constructs which may directly specify the execution ordering of ports. These constructs implement a path-expression-like mechanism for synchronisation and are also equipped with options to provide conditional, non-deterministic and priority ordering of ports. The usefulness and expressive power of the proposed concepts are illustrated through solutions of several representative programming problems. Some implementation issues are also considered.

Although incidence matrix representation has been used to analyze the Petri net based models of a system, it has the limitation that it does not preserve reflexive properties (i.e., the presence of self-loops) of Petri nets. But in many practical applications self-loops play very important roles. This paper proposes a new representation scheme for general Petri nets. This scheme defines a matrix called "reflexive incidence matrix (RIM) Cr," which is a combination of two matrices, a "base matrix Cb," and a "power matrix Cp." This scheme preserves the reflexive and other properties of the Petri nets. Through a detailed analysis it is shown that the proposed scheme requires less memory space and less processing time for answering commonly encountered net queries compared to other schemes. Algorithms to generate the RIM from the given net description and to decompose RIM into input and output function matrices are also given. The proposed Petri net representation scheme is very useful to model and analyze the systems having shared resources, chemical processes, network protocols, etc., and to evaluate the performance of asynchronous concurrent systems.

The stimulation technique has gained much importance in the performance studies of Concurrency Control (CC) algorithms for distributed database systems. However, details regarding the simulation methodology and implementation are seldom mentioned in the literature. One objective of this paper is to elaborate the simulation methodology using SIMULA. Detailed studies have been carried out on a centralised CC algorithm and its modified version. The results compare well with a previously reported study on these algorithms. Here, additional results concerning the update intensiveness of transactions and the degree of conflict are obtained. The degree of conflict is quantitatively measured and it is seen to be a useful performance index. Regression analysis has been carried out on the results, and an optimisation study using the regression model has been performed to minimise the response time. Such a study may prove useful for the design of distributed database systems.

Existing data-flow languages are incapable of supporting large, manageable and reliable non-deterministic programs. Operating system implementations and real-time applications require high-level non-deterministic programming facilities. Hoare's Communicating Sequential Processes and Brinch Hansen's Distributed Processes are two widely acclaimed distributed programming languages for conventional distributed computing systems. The powerful constructs of interprocess communication and synchronisation supported by the above two languages have been incorporated in Communicating Data Flow Channels (CDFC), and Distributed Data Flow Channels (DDFC), two languages proposed in this paper for distributed processing in data-flow systems. Several new features have been incorporated in these languages to make their execution more efficient in a data-flow environment. The implementation of these two languages on an abstract data-flow machine is investigated in detail. Two simulators have been implemented for testing the effectiveness of our implementation schemes for these two data-flow languages. These simulators are written in Pascal and run on a DEC 1090 computing system. This work demonstrates that a data-flow computing system can accommodate, without taking resort to specialised hardware units, the non-deterministic and synchronisation constructs of conventional languages with the attendant benefits of parallel data-driven execution.

Data flow computers are high-speed machines in which an instruction is executed as soon as all its operands are available. This paper describes the EXtended MANchester (EXMAN) data flow computer which incorporates three major extensions to the basic Manchester machine. As extensions we provide a multiple matching units scheme, an efficient, implementation of array data structure, and a facility to concurrently execute reentrant routines. A simulator for the EXMAN computer has been coded in the discrete event simulation language, SIMULA 67, on the DEC 1090 system. Performance analysis studies have been conducted on the simulated EXMAN computer to study the effectiveness of the proposed extensions. The performance experiments have been carried out using three sample problems: matrix multiplication, Bresenham's line drawing algorithm, and the polygon scan-conversion algorithm.

Assuming a horizontally distributed computing system, formulations of the edge-failure and node-failure recovery problems from the standpoint of load-leveling are presented. The conditions for the existence of solutions to these problems are examined and simple algorithms are proposed for these problems. In connection with the node-failure recovery problem, the concept of a node-failure metric to characterize different possible solutions is introduced, exploiting the notion of the strength of processors. A possible application of the recovery methods in the context of reconfiguration of distributed database systems is suggested.

Abstract Database management systems offer a very reliable and attractive data organization for fast and economical information storage and processing for diverse applications. It is much more important that the information should be easily accessible to users with varied backgrounds, professional as well as casual, through a suitable data sublanguage. The language adopted here (APPLE) is one such language for relational database systems and is completely nonprocedural and well suited to users with minimum or no programming background. This is supported by an access path model which permits the user to formulate completely nonprocedural queries expressed solely in terms of attribute names. The data description language (DDL) and data manipulation language (DML) features of APPLE are also discussed. The underlying relational database has been implemented with the help of the DATATRIEVE‐11 utility for record and domain definition which is available on the PDP‐11/35. The package is coded in Pascal and MACRO‐11. Further, most of the limitations of the DATATRIEVE‐11 utility have been eliminated in the interface package.