We describe how system design consistency can be maintained across multiple levels of design abstraction using a modular verification IP strategy. This strategy involves delivery of verification IP in an environment independent manner, utilizing a standard system verification architecture that leverages re-usable component verification drivers, transaction-based interfaces, and synchronization through a system-verification master. This enables a single test-bench to be applied for systems modeled both in SystemC, as well as at the RT level. The configuration of the verification testbench is kept consistent with the design by using system-design meta-data described using the specifications of The SPIRIT Consortium.

The increasing complexity of Systems on Chip (SoC) has introduced the need for abstract executable specifications (models) covering both hardware and embedded software. The new capabilities of SystemC 2.0, such as those added for transaction-based communication and test-bench Specification and monitoring, facilitate this SoC modeling. However, an obstacle to the adoption of abstract modeling as standard design practice is the lack of well establishes methodologies for the assessment of model precision. We describe such a methodology based on the SystemC Verification Standard implemented by Cadence's TestBuilder-SC. This methodology enables comparison of high-level (transaction level) SoC models in SystemC against implementation RTL models. An application of the methodology is presented, based on the AMBA Class Library (ACL) for SystemC being developed by ARM in collaboration with EDA partners. The key elements of the methodology are: 1. A completely reusable testbench that can be used for simulation and verification of the design at both high-level (transaction level) of abstraction and RTL implementation level. 2. A single database format is used so that data collected from simulations at each level can easily be processed and compared. We present an example of effective validation of ARM PrimeXsys-platform IP components against their RTL implementation.

We address the issue of standards development for the system-level design space. System-level design IP re-use standards are key to the future of the VSIA. However, the concept of system-level standards has its share of sceptics: what role can standards play in this developing market segment? In response we present an overview of three standards in the system-level VC integration space, and describe two distinct industrial case studies to support their practicality.

A technology dependent power optimization technique is proposed which formuhres the problem of hot spot reoktion as a variant of the engineering change (EC) problem A technique is presentedfor determining the sensitivity of circuit power dissipation tofunctional changer considering both local and global effects.This sensitivity is combined with a measure of synthesis jZexibility to identify hot regions in the circuit which have a lot offi'exibility in making functional changes andfor whom a small functional change can greatly @ect the overall power dissipation.An incompletely specified target function is constructed for the hot region such thnt any implementation sati.@ng it is expected to reduce power.A rewiring algorithm is used to solve the resulting EC problem without o#ecting circuit area, gate capacitance or delay under the unit delay mode.? Experimental results on a set of MCNC benchmark circuits show that the proposed approach con give up fo 13% reo'uction in power dissipotion with an average reaktion of 4%.

The Boolean space spanned by the primary input vectors of a combinational function may contain a large variance in minterm probabilities. By partitioning the Don't Care set into regions strongly and weakly influential upon switching activity we exploit this variance to bias area-optimization rewards reduced power dissipation. Experimental results indicate that our method can reduce power dissipation of a combinational CMOS circuit with no penalty in area.

There are three properties which define the global effect on power of a resynthesis step: change in function, change in spurious dynamic activity, and change in delay. In this paper, it is shown that the prediction of change in power due to change in functionality and change in spurious dynamic activity is accurate at high levels of estimator abstraction. Change in power due to change in delay is not. However, the magnitude of the effect of delay on power during resynthesis is shown to be the least critical of the three properties.