Media data delivery and processing such as telecommunications, networking, video processing, speech recognition and 3D graphics is increasing in importance and will soon dominate the processing cycles consumed in computer-based systems. This paper describes a processor called Linedancer, that provides high media performance with low energy consumption by integrating associative SIMD parallel processing with embedded microprocessor technology. The major innovations in the Linedancer is the integration of thousands of processing units in a single chip that are capable to support software programmable high-performance mathematical functions as well as abstract data processing. In addition to 4096 processing units, Linedancer integrates on a single chip a RISC controller that is an implementation of the SPARC architecture, 128 kbytes of data memory, and I/O interfaces. The SIMD processing in Linedancer implements the ASProCore architecture, which is a proprietary implementation of SIMD processing, operates at 266 MHz with program instructions issued by the RISC controller. The device also integrates a 64-bit synchronous main memory interface operating at 133 MHz (double-data rate, DDR), and a 64-bit 66 MHz PCI interface.

This paper presents an economics modelling tool for the analysis of MCM test and known good die strategies. The model calculates actual financial cost in parallel with quality at each stage from die manufacture to MCM assembly, test and rework, resulting in a powerful predictive tool for the evaluation of MCM test strategies. The spectrum of possible analyses which can be performed ranges from the evaluation of different KGD approaches to the analysis of alternative rework on a figure of merit basis. This is a novel approach to MCM strategies.

Associative processing architectures as candidates for second-generation massive parallel computers (MPCs) are discussed. The authors outline the principle of operation of associative processors, and briefly review their development. They explore the associative string processor (ASP) architecture as a representative case study in the development of a second-generation MPC.>