Interconnect synthesis techniques, such as wire sizing and buffer insertion/sizing, have proven to be critical for reducing interconnect delays in deep submicron design. Consequently, the past few years have seen several works that study buffer insertion, wire sizing, and their simultaneous optimization. For long interconnect, wire tapering, i.e., reducing the wire width as the distance from the driver increases, can yield better solutions than uniform wire sizing. However, despite its obvious benefits, tapering is not widely used in practice since it is difficult to integrate into a coherent routing methodology. This paper studies the benefits of wire sizing with tapering when combined with buffer insertion. We first present a theoretical result that shows wire tapering is at most 3.5% faster than uniform wire sizing when maximal buffer insertion is applied. We then present detailed experiments that support this result. Consequently, we conclude that it is generally not worthwhile to perform tapering for signal nets. Finally, we present a general formulation and optimal polynomial time algorithm for simultaneous wire sizing and buffer insertion that forbids wire tapering, but incorporates layer assignment and wire spacing.

An algorithm for unifying the techniques of gate sizing and clock skew optimization for acyclic pipelines is presented in this paper. In the design of circuits under very tight timing specifications, the area overhead of gate sizing can be considerable. The procedure described herein utilizes the idea of cycle borrowing using clock skew optimization to relax the stringency of the timing specification on the critical stages of the pipeline. The theoretical basis for the procedure is developed, a new algorithm for timing analysis of acyclic pipeline circuits with deliberate skew is presented, and a sensitivity-based optimizer is used to solve the sizing+skew problem. Our experimental results verify that the procedure of cycle borrowing using sizing+skew results in a better overall area-delay tradeoff as compared to using sizing alone.

An algorithm for unifying the techniques of gate sizing and clock skew optimization for acyclic pipelines is presented. In the design of circuits under very tight timing specifications, the area overhead of gate sizing can be considerable. The procedure utilizes the idea of cycle-borrowing using clock skew optimization to relax the stringency of the timing specification on the critical stages of the pipeline. Experimental results verify that cycle-borrowing using sizing+skew results in a better overall area-delay tradeoff than with sizing alone.

This paper describes a heuristic for speeding up combinational logic by decreasing the logic depth, at the expense of a minimal increase in circuit size. The heuristic iteratively speeds up sections of the critical path by the use of Shannon factorization on the late input. This procedure is empirically found to be capable of reproducing or even beating several classic global optimizations: a chain of an associative operator is transformed into a tree, a ripple prefix circuit into a parallel prefix circuit, and a ripple-carry adder into a slightly smaller and faster circuit than the carry-lookahead adder.

Improving the performance of a synchronous digital system by adjusting the path delays of the clock signal from the central clock source to individual flip-flops is investigated. Using a model to detect clocking hazards, two linear programs are investigated: (1) minimizing the clock period, while avoiding clock hazards, and (2) for a given period, maximizing the minimum safety margin against clock hazard. These programs are solved for a simple example, and circuit simulation is used to contrast the operation of a resulting circuit with the conventionally clocked version. The method is extended to account for clock skew caused by relative variations in the drive capabilities of N-channel versus P-channel transistors in CMOS.>

We describe an effort in applying database technology to the VLSI design process. By mixing software tools, relational database concepts, sophisticated index management, and existing VLSI design tools, we have built a flexible, interactive VLSI design system that provides data independence and technology independence. Design tools are interfaced with a centralized database to form an integrated design environment.

This paper describes the virtual grid compaction system provided by the IDA environment. The system facilitates the development and use of silicon generators, and supports their porting to new environments. A generator is a program that accepts parameters and produces good quality silicon layouts for small to medium size subcircuits, such as counters, registers, multipliers, etc. The system makes use of the “i” language for layout descriptions, the C language for algorithmic descriptions, a virtual grid to lambda grid compactor, and a tool for decompacting symbols so that they will match exactly, or with minimal routing between them. There are several ways to use the system, depending on the amount of flexibility needed. This system has been used to create a library of generators, and is flexible enough to handle a wide range of practical layout problems.

In this paper we investigate the ``mandatory-work-first'' approach to parallel alpha-beta search first proposed by Akl, Barnard, and Doran. This approach is based on a version of alpha-beta search without deep cutoffs and a two-stage evaluation process, the second stage of which is often pruned. Our analysis shows that for best-first ordering on the lookahead tree, this approach provides greater speedup than the Palphabeta tree-splitting technique, and that for worst-first ordering, mandatory work first provides only slightly worse speedup than Palphabeta.

A large-network algorithm solves a problem of size N on a network of N processors. We present a method for transforming certain large networks into quotient networks that emulate those large networks with fewer processors. Large-network algorithms are easily modified to execute on the quotient network. The emulations result in no loss in execution efficiency. Quotient networks allow algorithms to be designed assuming any number of processors and executed efficiently at a great savings in hardware cost.