We introduce the task of text-to-diagram generation, which focuses on creating structured visual representations directly from textual descriptions. Existing approaches in text-to-image and text-to-code generation lack the logical organization and flexibility needed to produce accurate, editable diagrams, often resulting in outputs that are either unstructured or difficult to modify. To address this gap, we introduce DiagramGenBenchmark, a comprehensive evaluation framework encompassing eight distinct diagram categories, including flowcharts, model architecture diagrams, and mind maps. Additionally, we present DiagramAgent, an innovative framework with four core modules—Plan Agent, Code Agent, Check Agent, and Diagram-to-Code Agent—designed to facilitate both the generation and refinement of complex diagrams. Our extensive experiments, which combine objective metrics with human evaluations, demonstrate that DiagramAgent significantly outperforms existing baseline models in terms of accuracy, structural coherence, and modifiability. This work not only establishes a foundational benchmark for the text-to-diagram generation task but also introduces a powerful toolset to advance research and applications in this emerging area.

Hand-drawn sketches are a natural and efficient medium for capturing and conveying ideas. Despite significant advancements in controllable natural image generation, translating freehand sketches into structured, machine-readable diagrams remains a labor-intensive and predominantly manual task. The primary challenge stems from the inherent ambiguity of sketches, which lack the structural constraints and semantic precision required for automated diagram generation. To address this challenge, we introduce SketchAgent, a multi-agent system designed to automate the transformation of hand-drawn sketches into structured diagrams. SketchAgent integrates sketch recognition, symbolic reasoning, and iterative validation to produce semantically coherent and structurally accurate diagrams, significantly reducing the need for manual effort. To evaluate the effectiveness of our approach, we propose the Sketch2Diagram Benchmark, a comprehensive dataset and evaluation framework encompassing eight diverse diagram categories, such as flowcharts, directed graphs, and model architectures. The dataset comprises over 6,000 high-quality examples with token-level annotations, standardized preprocessing, and rigorous quality control. By streamlining the diagram generation process, SketchAgent holds great promise for applications in design, education, and engineering, while offering a significant step toward bridging the gap between intuitive sketching and machine-readable diagram generation.

With the advanced technology used in the semiconductor manufacture process, systematic defects related to layout patterns and litho process are the major cause of yield issues. In this industry session, we invite three experts from three EDA companies to share their experiences of diagnosis and yield learning.

Cell-aware test is used to improve test quality and diagnosis accuracy. Simulation based cell-aware test model generation is a time consuming process. The overall characterization runtime of a standard cell is generally a function of pin count and the number of SPICE level devices. Exhaustive defect analysis requires unique simulations for each defect site across all cells in a library. Multi-bit cells have been widely adopted in low-power designs and they usually have both a large number of inputs, and SPICE level devices. This paper presents a general flow for cell-aware test model generation for clarity. We then propose a technique to speed-up the cell-aware defect model generation for multi-bit cells. Our evaluation on 16nm library cells shows the effectiveness of the proposed technique.

The health degree of large distributed information system reflected from the business perspective is the core index to measure the stability of information system. It has significant meaning for the fault diagnosis of any information system. To solve the above problems, a knowledge representation method based on weighted fault diagnosis is proposed in this paper. Based on the knowledge representation method, an information system fault diagnosis method based on weighted fault diagnosis tree is proposed. Then, a large distributed information system fault diagnosis model based on weighted fault diagnosis tree is established. Finally, an information system of medical industry is used to verify that the proposed method and model are efficient and practical, and it can provide quantitative means for the health of large distributed information system. In conclusion, the proposed method and model in the paper can find abnormal tendency and abnormal conditions of information system quickly and accurately, and provide performance assessment and fault early warning for large distributed information system.

Without appropriate stitching of scan chains, even with good diagnosis algorithm and diagnostic pattern generation, the chain diagnostic resolution may still be bad. In this paper, we propose a novel pattern-independent diagnosis and layout aware (DLA) scan chain stitching method: 1) the resolution is improved by increasing and properly distributing the sensitive scan cells, which can capture useful diagnostic information under both single- and multiple-fault situations; and 2) the scan cell layout placement is taken into account to reduce routing overhead and hence preserve the chip performance. Experiments using two different techniques to diagnose ISCAS'89/ITC'99 benchmark circuits with/without embedded scan compaction show the effectiveness of the proposed method in improving the diagnostic resolution. Impacts on chip performance, embedded scan compaction, transition fault coverage, and test power dissipation are negligible. The proposed method is also successfully applied to an industry circuit manufactured with 20-nm technology. The silicon results show 7× average resolution improvement comparing to without using the DLA scan chain stitching.

Without appropriate stitching of scan chains, even with good diagnosis algorithm and diagnostic pattern generation, it may still result in bad scan chain diagnostic resolution. To improve the diagnostic resolution, we propose a novel Diagnosis and Layout Aware (DLA) scan chain stitching method, which is pattern independent and supports embedded scan compaction. It is based on three ideas: (1) increasing the number of sensitive scan cells, which can capture useful diagnostic information; (2) properly distributing the sensitive scan cells along the scan chains to enhance the overall resolution; (3) stitching scan cells based on their placement at layout to preserve the chip performance. Experiments on ISCAS'89/ITC'99 benchmark circuits and a real industry circuit based on 20nm technology with silicon results show that, the proposed DLA scan chain stitching method effectively improves the resolution, with negligible impact on chip performance, embedded scan compaction, transition fault coverage, and test power dissipation. The silicon results even show 7X average resolution improvement comparing to without using the proposed method.

The Standard Delay Format (SDF) information is very important in timing-aware simulation of VLSI designs. However, conventionally, SDF is only design-dependent, but pattern-independent, which is called static SDF in this paper. Static SDF ignores all dynamic pattern dependent parameters, such as IR drop and crosstalk. In this paper, we propose a novel pattern-dependent SDF (called dynamic SDF) generation technique, and apply it to take IR-drop effects into consideration. With the proposed IR-drop-aware SDF generation technique, we improve the accuracy of simulation, and perform diagnosis on the failed patterns to pin point the pattern-dependent IR-drop defects in our design. Experimental results demonstrate the efficiency of this method when used for transition delay fault pattern application and diagnosis.

In this work, we propose a method to improve diagnosis results when multiple physical defects are present in circuits under diagnosis. To improve diagnosis results when multiple defects are present in a circuit under diagnosis, the proposed method includes (i) analyzing relations among locations of logic faults and their diagnostic metrics to carefully derive physical faults, (ii) a new set covering procedure and (iii) a method to assign scores to faults to derive candidate sets of faults. Experimental results on several industrial designs and several cases of silicon defects show the effectiveness of the proposed diagnosis method.

Speedpath debug is a critical step in improving clock frequency of a design to meet the performance requirement. However, speedpath debug based on functional patterns can be very expensive. In this paper, we explore scan-based speedpath debug techniques based on at-speed scan test patterns. Several enhancements are implemented to improve over an earlier proposed scan-based speedpath diagnosis algorithm. We further report the application results by applying the improved algorithm to a leading-edge high performance microprocessor design.

In the past, software based scan chain defect diagnosis can be roughly classified into two categories (1) model-based algorithms, and (2) data-driven algorithms. In this paper we first analyze the advantages and disadvantages of each category of the chain diagnosis algorithms. Next, an adaptive signal profiling algorithm that can use manufacturing ATPG scan patterns is proposed for scan chain diagnosis. Finally, several case studies and their PFA results are presented to validate the accuracy and effectiveness of the proposed algorithm.

In this paper, we present test generation procedures to improve scan chain failure diagnosis. The proposed test generation procedures improve diagnostic resolution by using multi-cycle scan test patterns. A diagnostic test generation flow to speed up diagnosis is proposed to address the issue of long run times of test generation and large number of test patterns for the cases where the range of suspected cells is large. Experimental results on several industrial designs show the effectiveness of the proposed procedures in improving diagnostic resolution, reducing run times of test generation and also reducing the number of test patterns.

An at-speed scan test methodology is proposed for the purpose of the timing optimization and calibration. The proposed method, called TOC-ATPG, addresses both undertesting and overtesting issues of the traditional at-speed scan-based structural test. A pseudo-random pattern-based circuit analysis is first applied to analyze the potential glitches and transitions due to the functional illegal states. A list of state elements to be constrained during ATPG to prevent the sensitization of the functional illegal transitions and glitches are derived. During ATPG the derived constraints are applied to prevent overtesting, and timing-aware transition fault approach is used simultaneously to detect the fault through the timing critical paths to overcome the undertesting issue. The proposed method demonstrates very high correlation to the purely sequential test in functional mode with bounded run time overhead and can be applied to very large design.

To reduce test data volumes, encoded tests and compacted test responses are widely used in industry. Use of test response compaction negatively impacts fault diagnosis since the errors in responses due to defects which are captured in scan cells are not directly observed. We propose a simple and effective way to enhance the diagnostic resolution achievable by production tests with minimal increase in pattern counts. In this work we present experimental results for the case of multiple scan chain faults to demonstrate the effectiveness of the proposed method.

Speed path debug is a critical step to improve the performance of high performance VLSI designs. The purpose of speed path debug is to identify the performance limiting paths and fix them in the next product stepping so that the chip can run at a higher clock frequency. This paper investigates speed path debug techniques using at-speed scan test patterns. For each failing scan cell, the failing paths are identified based on structural analysis of logic simulation values. We further propose two metrics to rank the identified speed paths based on logic value analysis and based on timing information calculated for the failing pattern. Experimental results show the effectiveness of the proposed speed path debug technique.

Primary/alternate version technique is a cost-effective means which trades the quality of computation results for promptness to tolerate the software faults. Generally speaking, this method requires that each real-time periodic task has two versions: primary and alternate. The primary version provides a result that is in some sense more desirable, but it may be subject to timing failure due to its complexity. On the contrary, the alternate version simply affords an acceptable service, but it could guarantee the timeliness owing to its simplicity. The kernel algorithm proposed in this paper employs the off-line backwards-RM scheme to pre-allocate time intervals to the alternate version and the on-line RM scheme to dispatch the primary version. Simulation results show that kernel algorithm provides higher success rate of primary version.

With nanometer processes, at-speed testing is required to filter out failing chips with delay defects to ensure high product quality. Locating delay defects is important not only for improving yield but also providing important information to enhance at-speed test methods to meet quality goals. In this paper, a method that leverages successful static defect diagnosis method to diagnose delay defects is presented. To avoid missing any defect suspects, transition fault model is used with special considerations of self masking, glitch detection and passing bit mismatch. The effectiveness of this approach is demonstrated with simulation experiments as well as two case studies on failing chips from Renesas Technology's 130nm process.

This paper describes a robust scan pattern mismatch debugger for the scan pattern validation process. Simulation mismatches observed during scan pattern validation process need to be resolved before scan pattern can be used in silicon. In this framework, we use efficient structural cone to create VCD values from a timing-based simulator. The VCD values are then used to trace the mismatches from failing observation points to the mismatch sources. Root-cause analysis is then performed by combining all mismatch source instances to conclude the most likely mismatch reasons. Comparing to existing solutions, the proposed mismatch debug flow doesnpsilat require VCD values of all signals in the designs, nor does it require multiple simulation of the test patterns in the Verilog simulator. Experimental results show the effectiveness and efficiency of the proposed scan pattern mismatch debug flow.

Prior effect-cause based chain diagnosis algorithms suffer from accuracy and performance problems when multiple stuck-at faults exist on the same scan chain. In this paper, we propose new chain diagnosis algorithms based on dominant fault pair to enhance diagnosis accuracy and efficiency. Several heuristic techniques are proposed, which include (1) double candidate range calculation, (2) dynamic learning and (3) two- dimensional space linear search. The experimental results illustrate the effectiveness and efficiency of the proposed chain diagnosis algorithms.

In this paper, we study the impact, detection and diagnosis of the defect inside a scan cell, which is called scan cell internal defect. We first use SPICE simulation to understand how a scan cell internal defect impacts the operation of a single scan cell. To study the detectability and diagnosability of a scan cell internal defect in a production test environment, we inject scan cell internal defects into a scan-based industrial design and perform fault simulation by using production scan test patterns. Next, we evaluate how effective an existing scan chain diagnosis technique based on traditional fault models can diagnose scan cell internal defect. We finally propose a new diagnosis algorithm to improve scan cell internal defect diagnostic resolution using scan cell internal fault model. Experimental results show the effectiveness of the proposed scan cell internal fault diagnosis technique.

In this paper, we present a fault dictionary based scan chain failure diagnosis technique. We first describe a technique to create small dictionaries for scan chain faults by storing differential signatures. Based on the differential signatures stored in a fault dictionary, we can quickly identify single stuck-at fault or timing fault in a faulty chain. We further develop a novel technique to diagnose some multiple stuck-at faults in a single scan chain. Comparing with fault simulation based diagnosis technique, the proposed fault dictionary based diagnosis technique is up to 130 times faster with same level of diagnosis accuracy and resolution.

In this paper, we present a test generation algorithm to improve scan chain failure diagnosis resolution. The proposed test generation algorithm creates a complete test set that guarantees each defective scan cell has unique failing behavior. This algorithm handles stuck-at fault and timing fault models. Problems and solutions that may happen in practical usage are discussed. We further extend the test generation algorithm to handle multiple failing scan chains and designs with embedded scan compression logic. Experimental results show the effectiveness of the proposed diagnostic test generation algorithm.

Scan based diagnosis can be of great help to guide physical failure analysis, which is critical for the success of silicon debug and yield ramp up. In practice, diagnosis becomes more difficult if scan chain defects and system logic defects co-exist on one die, which are called compound defects in this paper. We first describe the challenges in diagnosing this type of compound defects. A novel diagnosis flow is proposed to diagnose the compound defects on scan chain and system logic. The diagnosis methodology was successfully applied in industrial designs.

In this paper, we identify two main bottlenecks in the functional diagnosis flow and propose new ways to overcome these. Our approach completely eliminates the "primary input (PI) pattern generation and simulation" step and instead employs scan-dump values extracted from the tester. We utilize backward and forward logic implications of the scan-dump values to reconstruct more logic values for the circuit signals. Furthermore, we employ the reset state for the non-scan latches of the design to increase the number of specified signals in the overall circuit. Experimental results on stuck-at faults on industrial designs show that, in most cases, these reconstructed values are sufficient to correctly diagnose a fault, thereby avoiding hours of conventional functional diagnosis runtimes.

Production test data from more than 500,000 chips is analyzed to understand the correlation between the number of defective chips detected by a set of test patterns and the coverage values of these test patterns with respect to various test metrics. Experimental results show that the gate exhaustive metric has the highest correlation when compared to the stuck-at and the bridge coverage estimate metrics, especially for high coverage test patterns. More than 69% of all test patterns can be removed from the test set without reducing the number of detected chips - more than 99% of these patterns are required to obtain high stuck-at coverage. None of the test metrics are very effective in predicting which subset of a given set of test patterns can be removed from the test set without compromising test quality before the patterns are actually applied to manufactured ICs

This paper presents an algorithmic scan-chain-fault diagnosis procedure. The diagnosis for a single scan-chain fault is performed in three steps. The first step uses special chain test patterns to determine both the faulty chain and the fault type in the faulty chain. The second step uses a novel procedure to identify the suspect scan cell within a range of scan cells. The final step further improves the diagnostic resolution by ranking the suspect scan cells inside this range. The proposed technique handles both stuck-at and timing failures (transition faults and hold-time faults). The application of the procedure in a production test flow is discussed. Simulation and silicon results from several products show the effectiveness of the proposed method.

X-compactor is an X-tolerant test response compactor that is useful for massive reduction of test data volume and test time. This paper presents a technique for identifying failing flip-flops during scan test directly from the compacted response obtained from X-compactor outputs. The identified failing flip-flops can be used for several purposes - as inputs to a scan-based diagnosis tool to diagnose defects in combinational logic, to identify defective scan chains, or for statistical data collection during high volume manufacturing to analyze deformations and yield limiters. The presented technique requires no modification to existing scan-based diagnosis tools and has been used in high volume manufacturing flows. The experimental data from production test flows demonstrates its effectiveness for industrial designs.

The adoption of software platform is an effective method to resolve interoperability, portability, scalability and extensibility of open architecture controller. However, there exist problems in now available proprietary software platforms for OAC. Considering the successful application of CORBA, this paper presents the RTCK, a real-time middleware for OAC based on real-time CORBA and minimum CORBA. By the analysis of the feature of RTLinux and structure of OAC, RTCK is composed of user space and real-time space. The user space adopts open source, TAO; while real-time space conform to minimum CORBA, which uses leader/followers concurrent model and TLSF dynamic memory allocation algorithm to guarantee the real-time performance. In order to ensure the predictability of RTCK, SFIOP protocol based on Mbuff and real-time FIFO is designed, whose effect is verified by a comparative experiment.

This paper studies the impact of N-detect scan ATPG patterns on test quality and associated test costs. An incremental method for test generation is presented. Metrics to evaluate the richness of the test set are presented. The natural N-detect profiles of regular one-detect test sets and the impact to test data volume and test time of generating additional patterns is studied. Results are presented on an lntel/spl reg/ Pentium/spl reg/ 4 processor. Simulation results from evaluating the patterns on layout extracted and random bridges are presented. Silicon data from production test shows the effectiveness of N-detect tests.

Effective generation of diagnostic vectors can be assisted by a fast diagnostic fault simulator and an equivalence identification tool. Diagnostic fault simulation can be an expensive process for large circuits. If a large number of fault pairs are passed to an equivalence identification tool, it would take a long time. In this paper, a novel approach is proposed to concurrently execute diagnostic fault simulation and equivalence identification during diagnostic test generation, thereby reducing the overall execution time. Experimental results on industrial circuits and benchmark circuits demonstrate the potential of the proposed method.

We present a new static test sequence compaction procedure called reverse-order-restoration (ROR) for synchronous sequential circuits. It improves the efficiency of the basic vector restoration-based compaction procedure by reversing the order of the vectors in the original test sequence. This reduces the number of faults to be resimulated after every restoration step. We extend the ROR procedure to a class of radix reverse order vector restoration procedures. These procedures dynamically increase the number of vectors to be restored in each step and, thus, speed up the vector restoration process. We also investigate techniques to improve the compaction levels achieved by the ROR-based compaction procedure. By combining reverse order vector restoration and vector omission, higher compaction levels are achieved. Experimental results on test sequences generated by several test generators show the effectiveness of the proposed techniques.

We describe a property-based test generation procedure for synchronous sequential circuits. Several techniques are used to generate test sequences that achieve high fault coverages at low computational complexity. These include the use of static test compaction, input vector holding with optimal numbers of hold cycles, input vector perturbation, and identification of subsequences that are useful in extending the test sequence. Experimental results presented demonstrate that the proposed procedure achieves fault coverages which are in all cases the same or higher than those achieved by existing procedures.

We propose several techniques to improve a simulation based test pattern generation procedure for sequential circuits. The effectiveness of the proposed techniques is demonstrated through experimental results on a large set of benchmark circuits.

In this paper, we present a scan chain fault diagnosis procedure. The diagnosis for a single scan chain fault is performed in three steps. The first step uses special chain test patterns to determine both the faulty chain and the fault type in the faulty chain. The second step uses a novel procedure to generate special test patterns to identify the suspect scan cell within a range of scan cells. Unlike previously proposed methods that restrict the location of the faulty scan cell only from the scan chain output side, our method restricts the location of the faulty scan cell from both the scan chain output side and the scan chain input side. Hence the number of suspect scan cells is reduced significantly in this step. The final step further improves the diagnostic resolution by ranking the suspect scan cells inside this range. The proposed technique handles both stuck-at and timing failures (transition faults and hold time faults). The extension of the procedure to diagnose multiple faults is discussed. The experimental results show the effectiveness of the proposed method.

We describe a property based test generation procedure that uses static compaction to generate test sequences that achieve high fault coverages at a low computational complexity.A class of test compaction procedures are proposed and used in the property based test generator.Experimental results indicate that these compaction procedures can be used to implement the proposed test generator to achieve high fault coverage with relatively smaller run times.

The effect of test compaction on fault diagnosis is experimentally investigated. Results for combinational and sequential circuits indicate that the diagnostic resolution achieved by compacted tests is only minimally lower than that for uncompacted tests. Furthermore, the diagnostic resolution of the compacted tests can be enhanced to be the same or better than that for the uncompacted rests while still retaining compactness.

We describe a fault simulation based test generation procedure for synchronous sequential circuits. Several techniques are used to generate test sequences to achieve high fault coverages at low computational complexity. Experimental results presented demonstrate that the proposed procedure achieves fault coverages which are in all cases the same or higher than those achieved by existing procedures. The run times of the procedure are considerably smaller compared to the existing procedures.

We propose a new static test compaction procedure for synchronous sequential circuits. The procedure belongs to the class of procedures that omit test vectors from a given test sequence in order to reduce its length without reducing the fault coverage. The previous procedure that achieved high levels of compaction using this approach attempted to omit test vectors from a given test sequence one at a time or in subsequences of consecutive vectors. The omission of each vector or subsequence required extensive simulation to determine the effects of each omission on the fault coverage. The procedure proposed here first omits (almost) all the test vectors from the sequence, and then restores some of them as necessary to achieve the required fault coverage. The decision to restore a vector requires simulation of a single fault. Thus, the overall computational effort of this procedure is relatively low. The loss of compaction compared to the scheme that omits the vectors one at a time or in subsequences is small in most cases. Techniques to speed up the restoration process are also investigated, including consideration of several faults in parallel during restoration, and the use of a parallel fault simulator. Experimental results are presented to demonstrate the effectiveness of vector restoration as a static compaction technique.

We propose a technique to speed up restoration-based static test sequence compaction for synchronous sequential circuits. The proposed algorithm reverses the order of the test vectors during restoration. Specifically, every time a subsequence of T is restored to detect a subset of faults, the subsequence is placed at the end of the compacted sequence denoted by T/sub p/. In this way, a fault detected by T/sub p/ is guaranteed to remain detected by T/sub p/ at the end of the compaction process, and need not be resimulated as was the case with some of the earlier restoration based compaction methods. Experimental results presented in this paper demonstrate the effectiveness of the proposed procedure.

We propose several compaction procedures for synchronous sequential circuits based on test vector restoration. Under a vector restoration procedure, all or most of the test vectors are first omitted from the test sequence. Test vectors are then restored one at a time or in subsequences only as necessary to restore the fault coverage of the original sequence. Techniques to speed-up the restoration process are investigated. These include limiting the test vectors initially omitted from the test sequence, consideration of several faults in parallel during restoration, and the use of a parallel fault simulator.