As integration density increases, topology reconfiguration has emerged as a critical fault-tolerant technique for on-chip multiprocessors. To the best of our knowledge, existing methods for handling processor element (PE) faults in NoC-based multiprocessor arrays primarily target random faults, lacking effective strategies to handle clustered faults. To address this problem, this paper proposes a fast two-stage algorithm for constructing a high-performance, load-balanced logical topology. First, a diagonal-based fault replacement mechanism is introduced to minimize compensation paths for clustered faulty PEs. Second, an innovative candidate region selection strategy is proposed to replace faulty PEs, generating an initial topology with fewer row and column shifting operations. Finally, a novel Hawk-Tabu search algorithm is developed to further enhance communication performance through global search and local refinement of the logical topology. Experimental results show that, compared to state-of-the-art algorithms, the proposed approach reduces communication latency by an average of 10.01%, congestion by 10.37%, and fault-shifting hop count by 13.31% under a 64 × 64 topology with 7 × 7 clustered faults, while also achieving over 90% reduction in reconfiguration time. The proposed algorithms not only improve communication performance by alleviating latency and congestion issues but also enhance the efficiency of reconfiguration.

Fault-tolerant reconfiguration is essential for improving the reliability and efficiency of multiprocessor arrays. However, existing reconfiguration approaches primarily focus on algorithmic optimization, often neglecting architectural imbalance and communication bottlenecks arising from asymmetric redundancy placement. To overcome these limitations, this paper proposes an efficient framework that combines a novel double-sided redundant architecture with two-stage optimization algorithms to enhance interconnect efficiency under permanent processing element (PE) faults. The proposed$R_{l}+M+R_{r}$architecture symmetrically distributes redundant columns on both sides of the array while maintaining the same total number of spare PEs as single-sided redundancy, thereby mitigating unbalanced compensation paths and long communication distances without increasing hardware cost. Based on this structure, a shortest-path fault compensation algorithm is developed to minimize inter-PE communication distances, and a wide Tabu-based optimization algorithm is introduced as a second-stage refinement for global exploration and multi-directional reconfiguration. Experimental evaluations demonstrate that the proposed framework achieves superior communication performance and scalability compared with state-of-the-art methods under both single-sided and double-sided redundant architectures. It achieves lower latency, higher throughput, and reduced energy consumption while maintaining identical redundant resources and a smaller interconnect area footprint, confirming the efficiency and practicality of the proposed fault-tolerant topology reconfiguration strategy.

Three-dimensional (3-D) VLSI processor arrays offer high integration density and scalability, but their increasing system and interconnect complexity pose significant challenges to reliable reconfiguration under permanent hardware failures. Most existing reconfiguration approaches primarily target processing element (PE) faults and provide limited support for interconnect-related failures, such as switch and link faults, which can severely constrain feasible reconfiguration solutions and the achievable size of fault-free subarrays at the system level. This article investigates system-level fault-tolerant reconfiguration of reconfigurable 3-D VLSI processor arrays under multicomponent failures, including PE, switch, and link faults. We first analyze the system-level impact of different fault types and show that interconnect-level faults, especially switch failures, impose more pronounced constraints on reconfiguration effectiveness than PE faults. Based on this observation, a general plane-exclusion mechanism is introduced that can be integrated with representative PE-only reconfiguration schemes to enhance tolerance to switch and link failures. Furthermore, a fault-transformation preprocessing mechanism is developed to model switch failures as equivalent link disconnections, enabling unified system-level handling of heterogeneous faults and improving structural robustness. To mitigate excessive interconnect overhead introduced during reconfiguration, a long-interconnect optimization strategy is incorporated. Experimental results demonstrate that the proposed techniques significantly improve reconfiguration capability and scalability. In particular, the fault-transformation mechanism achieves over 90% of the theoretical upper bound in PE utilization under high switch fault densities, nearly doubling PE utilization compared with baseline methods, while the interconnect optimization reduces the number of long interconnects by more than 10% on average across all evaluated cases.

As the integration density of multiprocessor arrays increases, the likelihood of permanent faults in processing elements (PEs) rises, requiring effective topology reconfiguration for system reliability. However, existing router-based multiprocessor arrays reconfiguration methods predominantly rely on redundancy techniques and lack effective degradation strategies for applications of varying sizes. To address this, we propose a two-stage degradation-based topology reconfiguration algorithm to construct a maximized and high-performance logical array. First, we introduce a novel fault compensation mechanism by defining a set of faulty PE candidates to identify locally optimal fault-free PEs for compensation, minimizing the compensation path. Building upon this, we develop a greedy bidirectional column reconfiguration algorithm that constructs an initial fault-free logical array with short interconnects and prove its maximality. Lastly, we propose a satisfiability-based reconfiguration algorithm, transforming the topology reconfiguration problem into a satisfiability problem via a SAT model, reducing interconnect redundancy, and further optimizing array performance. Experimental results demonstrate that the proposed algorithm consistently outperforms state-of-the-art methods in reducing communication latency and alleviating link congestion, especially under high fault density conditions. Furthermore, as array size and fault density increase, the effectiveness of the proposed method becomes more pronounced, showcasing excellent scalability and robustness.

Background : Code-line-level bugginess identification (CLBI) is an important area within software quality assurance, aiming to pinpoint potential buggy source code lines in a given software product. Recently, two concurrent approaches, GLANCE and DeepLineDP, have showcased impressive performance by respectively leveraging syntactic and semantic features compared with the existing state-of-the-art (SOTA) approaches in this field. Problem : Yet, the literature lacks a thorough investigation that fuses these two types of features to enhance CLBI. Such fusion holds the promise of significantly improving the efficacy of identifying defective lines. Objective : We aim to advance CLBI by fusing syntactic and semantic features, thereby harnessing their respective strengths. Method : We propose to build a CLBI approach, booSting DeePLineDP wIth syntaCtic fEatures (SPLICE) , by fusing syntactic features from GLANCE and semantic features from DeepLineDP. SPLICE comprises three variants—SPLICE-S, SPLICE-G, and SPLICE-F—each utilizing a unique line-level sorting approach. We make a comprehensive comparison with the existing SOTA approaches using six performance metrics. Result : Through an analysis of nine open source projects, our experimental results reveal that SPLICE is competitive with current SOTA CLBI approaches. Notably, SPLICE-F demonstrates superiority over all SOTA CLBI approaches, including GLANCE and DeepLineDP, across all six metrics, indicating a substantial improvement. Conclusion : This discovery underscores the critical importance of future CLBI research in fusing syntactic and semantic features to construct more effective bugginess identification approaches. It is worth noting that the analysis was conducted within the context of Java programs, which highlights the potential for exploring similar methods in other programming languages in future research.

With the progressive augmentation of the density of 3-D processor arrays, some processor elements (PEs) often fail due to overload or overheating during massively parallel computing operations. Therefore, it is necessary to take effective fault-tolerant technology to ensure the reliability of the system. This article investigates an efficient reconfiguration method to construct 3-D fault-free logical subarray with more fault-free PEs and less interconnection length (interlength). First, we propose a novel method based on the barrel effect to find the bottleneck plane of 3-D processor arrays. Second, an efficient compensation strategy is proposed to replace faulty PEs on adjacent physical planes with fault-free PEs on the bottleneck planes, which leads to more fault-free PEs that can be used to construct the subarray. Then, we propose a heuristic to construct the subarray and optimize iteration redundancy to accelerate reconstruction. Finally, a heuristic optimization algorithm is proposed to reduce the interlength between PEs, which can reduce the dynamic power consumption and communication costs. In addition, we propose a more accurate method to calculate the lower bound of the interlength to better evaluate the performance of the algorithm. Simulation experiments show that, compared to the state-of-the-arts, on$128\times 128\times 128$host array, the utilization rate of fault-free PEs can be improved up to 15.6% and the interlength redundancy can be reduced by 78.2% for random faults. On$64\times 64\times 64$host array, the average improvement of the two indicators under clustered faults can reach 93.2% and 69.3%. Moreover, for all cases considered, the proposed new lower bound and reconstruction time can be reduced by an average of 18.47% and 76.13%, respectively.

With the ever-increasing integration and parallel computing capabilities of 3D processor arrays, the occurrence of processor elements (PEs) failures caused by various factors has become more prevalent. Therefore, the implementation of a fault-tolerant mechanism that uses the remaining fault-free PEs to reconfigure sub-array becomes critical. In this paper, we study the problem of reconfiguring a 3D subarray with as many fault-free PEs as possible, which has been shown to be NP-complete in previous work. Although prior algorithms have been effective under low fault densities, they are severely limited when faced with high fault densities. To address this, we first define the bottleneck of the 3D processor array, proposed a novel method to identify the physical bottleneck plane that restricts the reconfigurable size of the logical sub-array and prove its correctness. Then, we propose an effective compensation strategy that can fully utilize the fault-free PEs in the bottleneck plane. Under this strategy, a sliding-window weight calculation method is proposed to determine the priority of compensation. Finally, we proposed a heuristic algorithm, which can construct the maximum target array from different dimensions in polynomial time. Experimental results demonstrate that the proposed algorithm exhibits favorable performance in terms of harvest and degradation. For the random-failure model, the improvement in the harvest for fault-free PEs is up to 32.03% on a$32 \times 32 \times 32$host array with a 20% fault density. And for the clustered fault model, the improvement in harvest is up to 70.63% on a$32 \times 32 \times 32$host array distributed with 12 cluster failures of size$6 \times 6 \times 6$.

In this paper, we investigated the technique for improving the reliability of 3-D processor with faults by reconfiguring a 3-D fault-free subarray utilizing as many nonfaulty process elements (PEs) as possible. A novel flexible rerouting scheme is proposed, which makes the PEs can be rerouted or bypassed in three dimensions, hence increasing the number of neighbors of each element to construct a logical array. Under this scheme, an efficient heuristic algorithm is presented to construct a logical array. The experimental results show that the proposed algorithm under flexible rerouting scheme can produce logical arrays with higher harvest from the host arrays with faults for the random fault scenarios, the improvement is by up to 46.47% compared to the state-of-the-arts.