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Saied Bozorgui-Nesbat

dblp:54/4420 · DBLP profile ↗
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4ranked-venue papers
3as first author
0since 2021 · last 2003
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 2 first-authorHuman-computer interaction and ubiquitous computing · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
design for testability
0.021986
Lower Overhead Design for Testability of Programmable Logic Arrays · IEEE Trans. Computers 1986
Design for Autonomous Test · IEEE Trans. Computers 1981
Electronic design automation
hardware verification and test
0.021986
Lower Overhead Design for Testability of Programmable Logic Arrays · IEEE Trans. Computers 1986
Design for Autonomous Test · IEEE Trans. Computers 1981
Electronic design automation › hardware verification and test
fault coverage
0.011986
Lower Overhead Design for Testability of Programmable Logic Arrays · IEEE Trans. Computers 1986
Electronic design automation › hardware verification and test › VLSI testing
programmable logic array testing
0.011986
Lower Overhead Design for Testability of Programmable Logic Arrays · IEEE Trans. Computers 1986
Electronic design automation › hardware verification and test › design for testability
built-in self-test
0.011981
Design for Autonomous Test · IEEE Trans. Computers 1981

Methods — techniques the papers use, named apart from their topics

stuck-at fault modeling · 0.0network partitioning · 0.0exhaustive testing · 0.0
YearPublicationVenuePosition
2003 A system for fast, full-text entry for small electronic devices
abstract
A novel text entry system designed based on the ubiquitous 12-button telephone keypad and its adaptation for a soft keypad are presented. This system can be used to enter full text (letters + numbers + special characters) on devices where the number of keys or the keyboard area is limited. Letter-frequency data is used for assigning letters to the positions of a 3x3 matrix on keys, enhancing the entry of the most frequent Letters performed by a double-click. Less frequent letters and characters are entered based on a 3x3 adjacency matrix using an unambiguous, two-keystroke scheme. The same technique is applied to a virtual or soft keyboard layout so letters and characters are entered with taps or slides on an 11-button keypad. Based on the application of Fitts' law, this system is determined to be 67% faster than the QWERTY soft keyboard and 31% faster than the multi-tap text entry system commonly used on cell phones today. The system presented in this paper is implemented and runs on Palm OS PDAs, replacing the built-in QWERTY keyboard and Graffiti recognition systems of these PDAs.
Saied Bozorgui-Nesbat
ICMI1
1986 Lower Overhead Design for Testability of Programmable Logic Arrays
abstract
A new technique for designing easily testable PLA's is presented. The salient features of this technique are: 1) low overhead, 2) high fault coverage, 3) simple design, and 4) little or no impact on normal operation of PLA's. This technique consists of the addition of input lines in such a way that, in test mode, any single product line can be activated and its associated circuitry and device can be tested. Using this technique, all multiple stuck-at faults, as well as all multiple extra and multiple missing device faults, are detected.
Saied Bozorgui-Nesbat, Edward J. McCluskey
IEEE Trans. Computers1
1984 Lower Overhead Design for Testability of Programmable Logic Arrays
Saied Bozorgui-Nesbat, Edward J. McCluskey
ITC1
1981 Design for Autonomous Test
abstract
A technique for modifying networks so that they are capable of self test is presented. The major innovation is partitioning the network into subnetworks with sufficiently few inputs that exhaustive testing of the subnetworks is possible.
Edward J. McCluskey, Saied Bozorgui-Nesbat
IEEE Trans. Computers2