Demo Data from VLDB 2026 / reviewers in the wild / expert
Hans-Georg Osthof
dblp:54/5964
· DBLP profile ↗
3ranked-venue papers
0as first author
0since 2021 · last 1987
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Theory of computation · 2Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 50% Interconnection networks and networks-on-chip · 50% | |
| Theoretical computer science
1 paper |
Graph algorithms and graph theory · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › design methodology
hierarchical design |
0.0 | 1 | 1987 | Hierarchical Design Based on a Calculus of Nets · DAC 1987 |
Interconnection networks and networks-on-chip
network layout |
0.0 | 1 | 1987 | Layouts with Wires of Balanced Length · Inf. Comput. 1987 |
Graph algorithms and graph theory
graph layout |
0.0 | 1 | 1987 | Layouts with Wires of Balanced Length · Inf. Comput. 1987 |
Methods — techniques the papers use, named apart from their topics
algebraic specification · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1987 | Hierarchical Design Based on a Calculus of NetsabstractWe present an algebraic approach to hierarchical design of integrated circuits. This approach is based on a of nets which includes topological as well as behavioural aspects of integrated circuits. We have developed a hierarchical design system called CADIC which is build around this calculus in much the same way as e.g. Algol is build around numerics. An example for the design of a family of fast adders will demonstrate the power of this calculus. Finally we will give a summary outline on the structure of procedures which automatically transform the design into lower design levels. Bernd Becker 0001, Günter Hotz, Reiner Kolla, Paul Molitor, Hans-Georg Osthof |
DAC | 5 |
| 1987 | Layouts with Wires of Balanced Length
Bernd Becker 0001, Hans-Georg Osthof |
Inf. Comput. | 2 |
| 1985 | Layouts with Wires of Balanced Length
Bernd Becker 0001, Hans-Georg Osthof |
STACS | 2 |