Two important components of the concurrent simulation algorithm are divergence and scheduling. The effects of timing specifications in functional modules on divergence and scheduling are examined, and an efficient method for performing these operations is proposed. >

In this paper, two methods of applying two-pattern tests for stuck-open faults in scan-testable CMOS sequential circuits are presented. These methods require shifting in only one pattern and require no special latches in the scan chain. Sufficient conditions for 110bust testability of all single FET stuck-open faults and design techniques for robustly scan-testable CMOS sequential circuits are presented. These techniques lead to realizations with at most two additional inputs and some additional FETS in the first-level gates.

It is shown that the detectability of stuck-open faults in CMOS sequential circuits with scan paths containing ordinary shift register latches depends on the state assignment used. A method by which any state table can be realized by a circuit that is scan testable for stuck-open faults is presented. Tests can be applied to these circuits by shifting in only one vector per test, reducing the test application time. The proposed method is applied to five state tables from the MCNC Logic Synthesis and Optimization Benchmarks. It is found that the overhead of the method is in the range of 14% to 29%.>