Demo Data from VLDB 2026 / reviewers in the wild / expert
Ching-Lun Lin
dblp:54/6846
· DBLP profile ↗
4ranked-venue papers
1as first author
1since 2021 · last 2025
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-author · 1 since 2021Artificial intelligence and machine learning · 1 · 1 first-author · 1 since 2021Graphics, computer vision, multimedia, augmented reality and games · 1Human-computer interaction and ubiquitous computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Artificial intelligence
1 paper |
Image recognition and object detection · 77% Autonomous driving · 23% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Embedded and real-time systems · 79% Memory systems · 21% |
Topics — the 7 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Computer vision › Image recognition and object detection › object detection › object detection for autonomous driving
traffic sign detection |
0.9 | 1 | 2025 | TS-DETR: Traffic Sign Detection Based on Positive and Negative Sample Augmentation · ICRA 2025 |
Robotics › Autonomous driving
driver assistance |
0.3 | 1 | 2025 | TS-DETR: Traffic Sign Detection Based on Positive and Negative Sample Augmentation · ICRA 2025 |
Embedded and real-time systems › embedded software › embedded operating systems
embedded memory management |
0.2 | 1 | 2014 | CASA: Contention-Aware Scratchpad Memory Allocation for Online Hybrid On-Chip Memory Management · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2014 |
Embedded and real-time systems › embedded software › embedded operating systems › embedded memory management
scratchpad memory allocation |
0.2 | 1 | 2014 | CASA: Contention-Aware Scratchpad Memory Allocation for Online Hybrid On-Chip Memory Management · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2014 |
Memory systems
cache |
0.1 | 1 | 2014 | CASA: Contention-Aware Scratchpad Memory Allocation for Online Hybrid On-Chip Memory Management · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2014 |
Memory systems › cache
cache miss reduction |
0.1 | 1 | 2014 | CASA: Contention-Aware Scratchpad Memory Allocation for Online Hybrid On-Chip Memory Management · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2014 |
Embedded and real-time systems
energy-efficient embedded systems |
0.1 | 1 | 2014 | CASA: Contention-Aware Scratchpad Memory Allocation for Online Hybrid On-Chip Memory Management · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2014 |
Methods — techniques the papers use, named apart from their topics
negative sample learning · 0.9data augmentation · 0.9atrous pyramid pooling · 0.9DETR · 0.9
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | TS-DETR: Traffic Sign Detection Based on Positive and Negative Sample AugmentationabstractTraffic sign detection plays an essential role in advanced driver assistance system (ADAS) or self-driving vehicles. Typically, deep neural networks are employed to analyze road scene images captured by an onboard camera. However, due to the significant variation in appearance of different traffic signs, the classification of high similarity patterns is still a challenging task. To address these issues, this paper presents an end-to-end traffic sign detection framework based on DETR. The proposed network incorporates data augmentation and negative sample learning to mitigate the problem of data imbalance and enhance the model recognition capability effectively. An UASPP module (Upsample Atrous Pyramid Pooling) is introduced to integrate multi-scale features and global information. In the experiments, the performance evaluation has demonstrated the improvement of mAP by 3.9% on TT100K and 36.3% on GTSDB compared to state-of-the-art methods. The code and datasets are available at https://github.com/chinglun/TS-DETR. Ching-Lun Lin, Huei-Yung Lin, Chieh-Chih Wang |
ICRA | 1 |
| 2015 | EMG based rehabilitation systems - approaches for ALS patients in different stagesabstractFor the patients suffering from amyotrophic lateral sclerosis (ALS), they are encouraged to exercise their bodies routinely to prevent or delay the paralysis of muscles. This work proposes an electromyogram (EMG) based ALS rehabilitation system via playing computer games. The multi-channel EMG measuring system and the controlled interfaces to computer games were developed. According to the symptoms of disability, the controls from different muscles are designed. For ALS patients in the early stage, the EMG electrodes were placed on the forearm to detect the finger gestures; for ALS patients in the middle stage, the EMG signals of upper extremity were employed to detect the hand gestures and arm moving; for the late ALS stage, the EMG electrodes were placed on chin to detect the facial expression. A commercial video game as well as a self-modified computer game are utilized in our rehabilitation systems. We believe that the patients are more preferable to exercise their bodies in a form of entertainment. Yu-Lin Wang, Alvin Wen-Yu Su, Tseng-Ying Han, Ching-Lun Lin, Ling-Chi Hsu |
ICME | 4 |
| 2014 | CASA: Contention-Aware Scratchpad Memory Allocation for Online Hybrid On-Chip Memory ManagementabstractScratchpad memory (SPM) has been increasingly used in embedded systems due to its higher efficiency in terms of energy and area compared to that of ordinary cache. A hybrid on-chip memory architecture that combines SPM with a mini-cache has been proposed. One key issue for hybrid on-chip memory architectures is to reduce the number of off-chip memory accesses and energy consumption. Existing methods achieve this by moving the most frequently accessed data into SPM. However, these methods may be ineffective because the main source of off-chip memory accesses may not be the most frequently accessed data. Instead, most off-chip memory accesses are caused by cache misses, so reducing the latter will reduce the former. Cache misses are mainly caused by data contending for cache lines. Therefore, this paper proposes a contention-aware SPM allocation method for hybrid on-chip management. The number of cache misses for a page is used as a metric to determine whether a page should be moved to SPM. When the number of misses for a page exceeds a threshold, the page is moved to SPM, reducing cache contention. Experimental results show that the proposed method can reduce the energy delay product by 35% to 53% compared to a cache-only on-chip memory architecture and 19% to 31% compared to an existing hybrid on-chip memory architecture. Da-Wei Chang, Ing-Chao Lin, Yu-Shiang Chien, Ching-Lun Lin, Alvin Wen-Yu Su, Chung-Ping Young |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 4 |
| 2006 | A Collaborative Privacy-Enhanced Alibi Phone
Hsien-Ting Cheng, Ching-Lun Lin, Hao-Hua Chu |
GPC | 2 |