Byzantine Fault Tolerance (BFT) is crucial for ensuring the resilience of Distributed Machine Learning (DML) systems during training under adversarial conditions. Among the rising corpus of research on BFT in DML, there is no comprehensive classification of techniques or broad analysis of different approaches. This paper provides an in-depth survey of recent advancements in BFT for DML, with a focus on first-order optimisation methods, particularly, the popular one Stochastic Gradient Descent (SGD) during the training phase. We offer a novel classification of BFT approaches based on characteristics such as the communication process, optimisation method, and topology setting. This classification aims to enhance the understanding of various BFT methods and guide future research in addressing open challenges in the field. This work provides the foundations for developing robust BFT systems, using a variety of optimisation methods to strengthen resilience.

In this paper, we study how users can act as witnesses to limit the spread of fake news. We present a new technique based on consulting a set of users, called witnesses. Before resharing a content$M$by a user$A$, a set of$k$users (witnesses) are selected randomly, by the system, from the friends set of$A$. Witnesses are asked to validate the content$M$after allowing the user$A$to re-share it. If there is an authenticated user$AU$, among this set of witnesses that validating$M$, the user$A$is allowed to re-share it without considering the others$(k-1)$responses. In the case where all witnesses are non-authenticated, if at least one witness rejects the content$M$, the user$A$is not allowed to re-share it. Note that$A$has no knowledge about the set of selected witnesses.

This paper tackles the problem of locating the diffusion source in networks. Designating all nodes of the network as observers for locating the diffusion source is very complex and impracticable. To make this problem solvable in a simple manner, only a subset of nodes is used as observers. Choosing these observers can be a challenging task, as the effectiveness of the observers depends on various factors including the network topology, the diffusion process, and the available resources for observing the diffusion source. Several techniques have been proposed for selecting observers citing betweenness centrality, closeness centrality, high degree nodes, and randomization. This paper advances the state of the art by proposing the first solution, to our knowledge, for locating the diffusion source problem where the observers are selected as critical nodes.

Abstract Nowadays, cloud computing offers a digital infrastructure for smart city development. Cognitive cities are steadily automating daily urban processes. The ever expanding objective‐driven communities gather and share sensitive data that must be stored securely. Cloud computing offers a suitable platform that allows cognitive smart cities to access and re‐access data to learn from their past to adapt its current behaviour. However, the cloud is an untrusted entity that may expose data when decrypted for processing by systems. In this paper, we treat the issue of encrypted data processing. Often, the data is encrypted prior to transferring it to the cloud, where the cloud must have the data in clear to be able to make calculations which raises security and privacy threats if the cloud is considered untrusted. The scenario of asking users to make the calculations after decrypting the received cloud data and encrypting the obtained results before sending them back to the cloud is not a practical solution in distributed multi‐tenant architectures. Homomorphic encryption allows offers a solution for processing encrypted data. Many existing homomorphic encryption schemes suffer from limitations that hinder their usability. This paper presents an efficient fully homomorphic encryption scheme using twin key encryption and magic number fragmentation. The details of the scheme are presented along with cryptanalytic attacks to assess its effectiveness. The proposed scheme exhibits strong resilience against brute‐force attacks compared to its rivals from the literature. Finally, we illustrate the applicability of the proposed scheme using a cognitive smart city application.

This article is to propose a consensus algorithm, called Proof of Chance (PoCh), which is designed for the industrial Internet of Things (IIoT). The PoCh protocol is designed to be scalable and extensible, with a controllable conformance delay and low hardware and computation requirements. To reach a consensus, PoCh uses chance rather than computing power: “if condition$_{1}$, I am a candidate; if condition$_{2}$, I am the miner.” During every consensus iteration, the condition$_{1}$is updated, and a single miner is chosen using condition$_{2}$. Those conditions are randomized without the node generating any value and without assigning any weight to such value. The fault tolerance of PoCh is$5f/3 + 1$, meaning that PoCh can successfully achieve consensus as long as more than 40% of nodes are functioning properly, compared to 50% in the Proof of Stake (PoS) protocol.

Analog/RF built-in test (BIT) techniques are essential for reducing the very high costs of specification-based tests and for high-safety applications. The adoption of a BIT technique needs to be decided at the design stage, and this can be facilitated by estimating the test quality in terms of errors such as test escapes (TE) and yield loss (YL). Test quality estimation at the design stage has been traditionally very difficult for analog/RF circuits due to the lack of fault models that properly cover parametric faulty behavior. In recent years, statistical simulation has been considered in combination with learning techniques for the estimation of parametric test metrics. Extreme value theory (EVT) has provided a rigorous tool for the computation of parametric test metrics. However, test metrics estimation has been limited to the use of a univariate model. In this paper, we extend this approach by using a multivariate extreme value model. We illustrate this for the evaluation of an RF LNA BIT technique using a bivariate model.

A leader node in Ad hoc networks and especially in WSNs and IoT networks is needed in many cases, for example to find a node with minimum energy or situated on the extreme left of the network. For this kind of applications, algorithms must be robust and fault-tolerant since it is difficult and even impossible to intervene if a node fails. Such a situation can be catastrophic in case that this node is the leader. In this paper, we present a new algorithm, which is based on a tree routing protocol. It starts from local leaders which will start the process of flooding to determine a spanning tree. During this process their value will be routed. If two spanning trees meet each other then the tree routing the best value will continue its process while the other tree will stop it. The remaining tree is the dominating one and its root will be the leader. This algorithm turns out to be low energy consuming with reduction rates that can exceed 85%. It is efficient and fault-tolerant since it works in the case where any node can fail and in the case where the network is disconnected.

The number of connected devices is growing and in the near future it is expected to become extremely large in cities. As a consequence, using simulators to study and prepare a project of installing new networks before their real deployment is of great importance. They can help to predict some important information like signal overload or the feasibility of the deployment in terms of location, interferences, communication and cost. In this paper we present a new architecture for the platform CupCarbon, developed within the research project PERSEPTEUR. The main objective of this platform is to design and simulate Wireless Sensor Networks dedicated to Smart-city and IoT applications. It allows to validate distributed algorithms in a 2D/3D environment, taking account of the city buildings in which to deploy the network, the mobiles, and using accurate models of radio propagation and interferences in that environment.

In the new generation of networks, not only computers are connected but also objects like cars, streets, buildings, or just, everything. In general, these things communicate by means of internet using gateways. Simulating these systems can help to validate specific algorithms and concepts. However, it cannot give any accurate information about reality when some problems arise such as delays, disconbectivity, attacks, insecurity, and especially in the case of large networks. Also, the real implementation of such networks is very complex, time consuming and can be impossible when the nodes are situated in different cities or countries. In this demo we propose a new platform called CupCarbon-Lab based on the existing simulator CupCarbon, where the codes used in simulation can be directly injected in real connected embedded cards like Raspberry Pi cards. This platform can automatically generate from the software a real IoT network even it is already deployed, which can be reconfigured without the need to go through each node. It also helps to test the feasibility and the scalability of an algorithm in real conditions.

The Leader Election in Wireless Sensor Networks depends on the nature of the application domain, the use case and the energy consumption. In the case of real time applications, the choice will be based on the speed of the election, and in the case where time is not important, the choice will be based on the energy consumption. The classical algorithm allowing to elect such a node is called the Minimum Finding Algorithm. In this algorithm, each node sends its value in a broadcast mode each time a better value is received. This process is very energy consuming and not reliable since it is subject to an important number of collisions and lost messages. In this paper, we propose a new algorithm called BROGO (Branch Optima to Global Optimum) where after finding a spanning tree of a WSN, each leaf will route a message through its branch to the root in order to find the leader in that branch. The root will then elect the global leader from the received branch leaders. This process is more reliable since there is a small number of broadcast messages and a reduced number of nodes that send broadcast messages at the same time. The obtained results show that the proposed algorithm reduces the energy consumption with rates that can exceed 95% when compared with the classical Minimum Finding Algorithm. Its message and time complexity is equal to O(n).

Wireless Sensor Networks (WSNs) are an important tool for monitoring strategic and dangerous sites where high security is required. Failure detection for sensor nodes in this specified application is a major concern. The failure of any system may cause losses such as economical, equipment damage and even risks for human lives. Moreover, failures are unavoidable in WSNs due to hardware constraints, hostile environment, unattended deployment and limited resources. This paper proposes a fully distributed approach, called Boundary Node Failure Detection (BNFD), for an efficient boundary control based on the determination of the WSN boundary. This one is determined using an algorithm which has the property to determine in each iteration the one-hop neighbor of the current boundary sensor. Hence, each boundary sensor knows its direct next boundary neighbor and can communicate with it in order to periodically test its presence. When a situation of failure is detected, a network restructuring will be launched to find a new boundary and an alarm will be triggered. The proposed approach has been implemented and simulated with the Castalia simulator. The simulation results show that the proposed method is energy efficient.

IEEE 802.15.4 protocol is very much associated with ZigBee protocol and targets low data rate, low power consumption and low cost wireless networking that fits the requirements of wireless sensor networks (WSNs). Due to increase in radio frequency (RF) based communication devices and spectrum sharing between these devices makes it impossible to neglect the affect of interference on wireless communications. This paper provides brief description about technical features of IEEE standard 802.15.4 and ZigBee based physical layer structure and wireless channel impulsive interference modeling for wireless sensor networks in smart cities applications. For more accurate estimation of wireless channel characteristics, we have modeled it using alpha-stable distribution function. We have then estimated two out of four parameters of alpha-stable distribution depending on spatial density of wireless devices in specified area around the wireless node in a network. This allows better modeling and estimation of wireless channel conditions. We have analyzed IEEE standard 802.15.4 based communication system performance in terms of the bit error rate (BER). We have varied the total number of active nodes in specified area around sensor node and evaluates its affect on overall BER performance. We have also integrated this PHY layer based on IEEE standard 802.15.4 in the CupCarbon simulator with the consideration of impulsive network interference and its modeling using alpha-stable distribution.

Testing analog integrated circuits is expensive in terms of both test equipment and time. To reduce the cost, Design-For-Test techniques (DFT) such as Built-In Self-Test (BIST) have been developed. For a given Circuit Under Test (CUT), the choice of a suitable technique should be made at the design stage as a result of the analysis of test metrics such as test escapes and yield loss. However, it is very hard to carry out this estimation for analog/RF circuits by using fault simulation techniques. Instead, the estimation of parametric test metrics is made possible by Monte Carlo circuit-level simulations and the construction of statistical models. These models represent the output parameter space of the CUT in which the test metrics are defined. In addition, models of the input parameter space may be required to accelerate the simulations and obtain higher confidence in the DFT choices. In this work, we describe a methodological flow for the selection of most adequate statistical models and several techniques that can be used for obtaining these models. Some of these techniques have been integrated into a Computer-Aided Test (CAT) tool for the automation of the process of test metrics estimation. This estimation is illustrated for the case of a BIST solution for CMOS imager pixels that requires the use of advanced statistical modeling techniques.

This paper proposes a new technique for the optimization of multi-frequency tests for linear analog circuits. Fault simulation is used to obtain the frequency intervals for the detection of each fault. New efficient algorithms are then presented for the selection of the optimal set of test frequencies within these intervals for the detection of all faults. Numerical simulations with randomly generated problem instances demonstrate the good time complexity of the proposed algorithms, with a large improvement over previous approaches (Mir et al 1996).

In this paper we show that the problem of minimizing the number of test frequencies necessary to detect all possible faults in a multi-frequency test approach for linear analog circuits can be modeled as a set covering problem. We will show in particular, that under some conditions on the considered faults, the coefficient matrix of the problem has the strong consecutive-ones property and hence the corresponding set covering problem can be solved in polynomial time. For an efficient solution of the problem, an interval graph formulation is also used and a polynomial algorithm using the interval graph structure is suggested. The optimization of test frequencies for a case-study biquadratic filter is presented for illustration purposes. Numerical simulations with a set of randomly generated problem instances demonstrate two different implementation approaches to solve the optimization problem very fast, with a good time complexity.

A new technique for the estimation of analog parametric test metrics at the design stage is presented in this paper. This technique employs the copulas theory to estimate the distribution between random variables that represent the performances and the test measurements of the circuit under test (CUT). A copulas-based model separates the dependencies between these random variables from their marginal distributions, providing a complete and scale-free description of dependence that is more suitable to be modeled using well-known multivariate parametric laws. The model can be readily used for the generation of an arbitrarily large sample of CUT instances. This sample is thereafter used for estimating parametric test metrics such as defect level (or test escapes) and yield loss. We demonstrate the usefulness of the proposed technique to evaluate a built-in-test technique for a radio frequency low noise amplifier and to set test limits that result in a desired tradeoff between test metrics. In addition, we compare the proposed technique with previous ones that rely on direct density estimation.

The reduction of analog/RF production test costs calls for the optimization of specification-based tests or their replacement by low-cost ones. A variety of techniques have been proposed in recent years, such as specification-based test ordering and compaction, alternate test to predict the specified performances from simpler measurements, and on-chip circuitry to monitor IC performance while alleviating the complexity of test equipment. Since statistical evidence about test quality can only be gathered from large volume production test data, most innovative test techniques fail to gain acceptance for real products. This is because by the time this evidence could be obtained, most test costs would have already been engaged. At this stage, the change of the test procedure would hardly be acceptable and the modification of the design is no longer possible.

We present a method that is capable of handling process variations to evaluate analog/RF test measurements at the design stage. The method can readily be used to estimate test metrics, such as parametric test escape and yield loss, with parts per million accuracy, and to fix test limits that satisfy specific tradeoffs between test metrics of interest. Furthermore, it provides a general framework to compare alternative test solutions that are continuously being proposed toward reducing the high cost of specification-based tests. The key idea of the method is to build a statistical model of the circuit under test and the test measurements using nonparametric density estimation. Thereafter, the statistical model can be simulated very fast to generate an arbitrarily large volume of new data. The method is demonstrated for a previously proposed built-in self-test measurement for low-noise amplifiers. The result indicates that the new synthetic data have the exact same structure of data generated by a computationally intensive brute-force Monte Carlo circuit simulation.

Pseudorandom test techniques are widely used for measuring the impulse response (IR) for linear devices and Volterra kernels for nonlinear devices, especially in the acoustics domain. This paper studies the application of pseudorandom functional test techniques to linear and nonlinear MEMS built-in-self-test (BIST). We will first present the classical pseudorandom BIST technique for linear time invariant (LTI) systems which is based on the evaluation of the IR of the device under test (DUT) stimulated by a maximal length sequence (MLS). Then we will introduce a new type of pseudorandom stimuli called the inverse-repeat sequence (IRS) that proves better immunity to noise and distortion than MLS. Next, we will illustrate the application of these techniques for weakly nonlinear, purely nonlinear and strongly nonlinear devices

This paper introduces a computer-aided-test platform that has been developed for the evaluation of test techniques for analogue and mixed-signal circuits. The CAT platform, integrated in the Cadence design framework environment, includes tools for fault simulation, test generation and test optimization for these types of circuits. Fault modeling and fault injection are simulator independent, which makes this approach flexible with respect to past approaches. In this paper, the use of this platform is illustrated for test optimization for the case of a fully differential amplifier. Test limits are set using a statistical circuit performance analysis that accounts for process deviations. Test metrics are estimated using this analysis. Specification-based tests are next optimized in terms of their capability of detecting catastrophic faults

The production test of CMOS image sensors is complicated and expensive as an electrical and an optical test must be executed for the pixel matrix. In this paper we study a built-in-self-test (BIST) technique for the pixels. The technique is based on applying a voltage stimulus at the photosensitive element of the image sensor. The aim of this work is to avoid light stimuli to realise an only electrical test to determine if a pixel is functional or not. This will then reduce test time and test cost. To quantify the quality of this test approach, test metrics such as fault rejection and fault acceptance are estimated. Catastrophic and parametric faults are taken into consideration for the estimation of the test quality

The test of high resolution sigma-delta analogue-to-digital converters (SigmaDelta ADCs) is a costly task due to its high resolution and the large number of samples required. In this paper, we propose a built-in self-test (BIST) technique for the test of SNDR (signal-to-noise plus distortion ratio) in SigmaDelta ADCs. The technique, mostly digital, uses a binary stream as test stimulus and carries out a sine-wave fitting algorithm to analyse the output response. Both the test signal generation and the output response analysis are performed on-chip, taking advantage of the digital resources already present in a SigmaDelta ADC. Simulations results show the capability of this technique to obtain measures of the SNDR for a 16-bit audio SigmaDelta ADC

The test of analogue and mixed-signal (AMS) cores requires the use of expensive AMS testers and accessibility to internal analogue nodes. The test cost can be considerably reduced by the use of built-in-self-test (BIST) techniques. One of these techniques consists of generating analogue test signals from digital test patterns (obtained via /spl Sigma//spl Delta/ modulation) and converting the responses of the analogue modules into digital signatures that are compared with the expected ones. This paper presents an implementation of the analogue test signal generation part that includes programmability of the circuit blocks, leading to an improvement of performance and a reduction of circuit size with respect to previous approaches. A 0.18 /spl mu/m CMOS circuit has been designed and fabricated, allowing the generation of test signals ranging from 10 Hz to 1 MHz.