The unified modeling language (UML) 2.0 is emerging in the area of embedded system design. This paper presents a new UML 2.0 profile - called TUT-profile - that introduces a set of stereotypes and design rules for an application, platform, and mapping. The profile classifies different application and platform components, and enables their parameterization. The TUT-profile concentrates on the structure of an application and platform, and utilizes standard UML 2.0 for the behavioral modeling. The application is seen as a set of active classes with an internal behavior. Correspondingly, the platform is seen as a component library with a parameterized presentation in UML 2.0 for each library component.

The concept of data flow computing is applied to digital signal processing (DSP). A data flow signal processor (DFSP) architecture is presented. The principles of data flow computing are carefully considered in order to conform with the special properties of DSP. The bus oriented architecture is easily configured to meet various performance requirements. The DFSP architecture is most suitable for nonrecursive algorithms. Typical tasks of this nature are transforms and FIR filters. A simulation model of the DFSP architecture has been developed. Simulation results of two application examples are given.

The architecture of the Data Flow Signal Processor (DFSP) is discussed with the emphasis on its control mechanism. It is argued that the data flow principle can be efficiently applied to block processing operations of nonrecursive DSP computations, when shared data structures are avoided. Simulation results involving the optimal operand size and the memory use of the control section are presented. Due to the expandability and convenient programmability of the DFSP architecture, the range of its potential applications extends beyond signal processing as demonstrated by a DFSP based database machine.

A new architecture based on the data flow principle has been developed for signal processing purposes. The Data Flow Signal Processor (DFSP) is capable of highly parallel computation of block realizations of nonrecursive algorithms. The flexibility and modularity of the DFSP architecture are illustrated by two examples. The three-sensor problem shows the high performance of the DFSP in handling three 100 kHz input streams and performing correlation computations on them. The second example shows that 256 × 256 images can be processed with spatially restricted operations at video rate.