The paper discusses the architecture and performance of a prototype RISC multi-processor server designed for a business system like OLTP (online transaction processing). The combination of a low-latency cache-to-cache copy and an 8-way highly interleaved main memory realize high performance for the OLTP program. We analyzed the activity of the multi-processor system when executing the OLTP program by using the trace-driven simulator including kernel execution. The main findings are that: cache misses due to task migration and ping-ponging of kernel shared data occupy a larger part of the total misses, especially in a large cache capacity because of intensive I/O activities; and the low-latency cache-to-cache copy is very effective because 50-60% of the data read accesses are supplied by the cache-to-cache copy in a large cache capacity.>

Cache memory architectures and BiCMOS circuit technologies for high-speed access time that take advantage of the high integration level are discussed. Proposed is a VLSI-oriented cache memory architecture, which reduces the penalty of chip-crossings, and a functional BiCMOS RAM with gate-array suited to the associative function of the cache memory. BiCMOS cache chip sets are developed for high-performance computers with 0.8- mu m BiCMOS technology. The BiCMOS cache memory can improve the cost-performance of cache systems due to high-speed access time and high density.>

This paper discusses an optimal memory system to realize a high performance integrated Prolog processor, the IPP. First, the memory access characteristics of Prolog are analyzed by a simulator, which simulates the execution of a Prolog program at a micro instruction level. The main findings from this analysis are that: the write access ratio of Prolog is larger than that of procedural languages; and performance improvement requires the memory system to process concentrated, large write accesses effectively.